riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[FPGA-Bitstream] Add a new data structure that stores fabric bitstream for memory bank using shift registers

This commit is contained in:
tangxifan 2021-09-30 17:01:02 -07:00
parent 43c569b612
commit 4526133089
3 changed files with 193 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

77
openfpga/src/fpga_bitstream/memory_bank_shift_register_fabric_bitstream.cpp Normal file
View File

@ -0,0 +1,77 @@
#include "vtr_assert.h"
#include "memory_bank_shift_register_fabric_bitstream.h"
/* begin namespace openfpga */
namespace openfpga {
MemoryBankShiftRegisterFabricBitstream::word_range MemoryBankShiftRegisterFabricBitstream::words() const {
return vtr::make_range(bitstream_word_ids_.begin(), bitstream_word_ids_.end());
}
size_t MemoryBankShiftRegisterFabricBitstream::num_words() const {
return bitstream_word_ids_.size();
}
size_t MemoryBankShiftRegisterFabricBitstream::word_size() const {
/* For a fast runtime, we just inspect the last element
* It is the validator which should ensure all the words have a uniform size
*/
return bitstream_word_bls_[bitstream_word_ids_.back()].size();
}
size_t MemoryBankShiftRegisterFabricBitstream::bl_width() const {
/* For a fast runtime, we just inspect the last element
* It is the validator which should ensure all the words have a uniform size
*/
return bitstream_word_bls_[bitstream_word_ids_.back()].back().size();
}
size_t MemoryBankShiftRegisterFabricBitstream::wl_width() const {
/* For a fast runtime, we just inspect the last element
* It is the validator which should ensure all the words have a uniform size
*/
return bitstream_word_wls_[bitstream_word_ids_.back()].back().size();
}
std::vector<std::string> MemoryBankShiftRegisterFabricBitstream::bl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id) const {
VTR_ASSERT(valid_word_id(word_id));
return bitstream_word_bls_[word_id];
}
std::vector<std::string> MemoryBankShiftRegisterFabricBitstream::wl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id) const {
VTR_ASSERT(valid_word_id(word_id));
return bitstream_word_wls_[word_id];
}
MemoryBankShiftRegisterFabricBitstreamWordId MemoryBankShiftRegisterFabricBitstream::create_word() {
/* Create a new id*/
MemoryBankShiftRegisterFabricBitstreamWordId word_id = MemoryBankShiftRegisterFabricBitstreamWordId(bitstream_word_ids_.size());
/* Update the id list */
bitstream_word_ids_.push_back(word_id);
/* Initialize other attributes */
bitstream_word_bls_.emplace_back();
bitstream_word_wls_.emplace_back();
return word_id;
}
void MemoryBankShiftRegisterFabricBitstream::add_bl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id,
const std::string& bl_vec) {
VTR_ASSERT(valid_word_id(word_id));
VTR_ASSERT(bl_vec.size() == bl_width());
return bitstream_word_bls_[word_id].push_back(bl_vec);
}
void MemoryBankShiftRegisterFabricBitstream::add_wl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id,
const std::string& wl_vec) {
VTR_ASSERT(valid_word_id(word_id));
VTR_ASSERT(wl_vec.size() == wl_width());
return bitstream_word_wls_[word_id].push_back(wl_vec);
}
bool MemoryBankShiftRegisterFabricBitstream::valid_word_id(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id) const {
return ( size_t(word_id) < bitstream_word_ids_.size() ) && ( word_id == bitstream_word_ids_[word_id] );
}
} /* end namespace openfpga */

93
openfpga/src/fpga_bitstream/memory_bank_shift_register_fabric_bitstream.h Normal file
View File

@ -0,0 +1,93 @@
#ifndef MEMORY_BANK_SHIFT_REGISTER_FABRIC_BITSTREAM_H
#define MEMORY_BANK_SHIFT_REGISTER_FABRIC_BITSTREAM_H
#include <string>
#include <map>
#include <vector>
#include "vtr_vector.h"
#include "memory_bank_shift_register_fabric_bitstream_fwd.h"
/* begin namespace openfpga */
namespace openfpga {
/******************************************************************************
* This files includes data structures that stores a downloadable format of fabric bitstream
* which is compatible with memory bank configuration protocol using shift register to control BL/WLs
* @note This data structure is mainly used to output bitstream file for compatible protocols
******************************************************************************/
class MemoryBankShiftRegisterFabricBitstream {
public: /* Types */
typedef vtr::vector<MemoryBankShiftRegisterFabricBitstreamWordId, MemoryBankShiftRegisterFabricBitstreamWordId>::const_iterator word_iterator;
/* Create range */
typedef vtr::Range<word_iterator> word_range;
public: /* Accessors: aggregates */
word_range words() const;
public: /* Accessors */
/* @brief Return the length of bitstream */
size_t num_words() const;
/* @brief Return the length of each word. All the word should have a uniform size */
size_t word_size() const;
/* @brief Return the width of each BL word, which is the number of heads through which a BL word can be loaded in parallel */
size_t bl_width() const;
/* @brief Return the width of each WL word, which is the number of heads through which a WL word can be loaded in parallel */
size_t wl_width() const;
/* @brief Return the BL vectors with a given word id*/
std::vector<std::string> bl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id) const;
/* @brief Return the WL vectors in a given word id */
std::vector<std::string> wl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id) const;
public: /* Mutators */
/* @brief Create a new word */
MemoryBankShiftRegisterFabricBitstreamWordId create_word();
/* @brief Add BLs to a given word */
void add_bl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id,
const std::string& bl_vec);
/* @brief Add WLs to a given word */
void add_wl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id,
const std::string& wl_vec);
public: /* Validators */
bool valid_word_id(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id) const;
private: /* Internal data */
/* Organization of the bitstream
*
* ============= Begin of Word 1 ==============
* |<--No of -->|<-- No of -->|
* | BL heads | WL heads |
* 010101 .. 101 101110 .. 001 ----
* ... ... ^
* |
* max. shift register length per word
* |
* v
* 110001 .. 111 100100 .. 110 ----
* ============= End of Word 1 ==============
* ============= Begin of Word 2 ==============
* 010101 .. 101 101110 .. 001 ----
* ... ... ^
* |
* max. shift register length per word
* |
* v
* 110001 .. 111 100100 .. 110 ----
* ============= End of Word 2 ==============
* .... more words
*/
vtr::vector<MemoryBankShiftRegisterFabricBitstreamWordId, MemoryBankShiftRegisterFabricBitstreamWordId> bitstream_word_ids_;
vtr::vector<MemoryBankShiftRegisterFabricBitstreamWordId, std::vector<std::string>> bitstream_word_bls_;
vtr::vector<MemoryBankShiftRegisterFabricBitstreamWordId, std::vector<std::string>> bitstream_word_wls_;
};
} /* end namespace openfpga */
#endif

23
openfpga/src/fpga_bitstream/memory_bank_shift_register_fabric_bitstream_fwd.h Normal file
View File

@ -0,0 +1,23 @@
/**************************************************
* This file includes only declarations for
* the data structures for MemoryBankShiftRegisterFabricBitstream
* Please refer to memory_bank_shift_register_fabric_bitstream.h for more details
*************************************************/
#ifndef MEMORY_BANK_SHIFT_REGISTER_FABRIC_BITSTREAM_FWD_H
#define MEMORY_BANK_SHIFT_REGISTER_FABRIC_BITSTREAM_FWD_H
#include "vtr_strong_id.h"
/* begin namespace openfpga */
namespace openfpga {
/* Strong Ids for ModuleManager */
struct memory_bank_shift_register_fabric_bitstream_word_id_tag;
typedef vtr::StrongId<memory_bank_shift_register_fabric_bitstream_word_id_tag> MemoryBankShiftRegisterFabricBitstreamWordId;
class MemoryBankShiftRegisterFabricBitstream;
} /* end namespace openfpga */
#endif