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[FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object

This commit is contained in:
tangxifan 2021-09-30 14:47:21 -07:00
parent 4d8019b7c1
commit 43c569b612
5 changed files with 155 additions and 21 deletions
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50
openfpga/src/fpga_bitstream/memory_bank_flatten_fabric_bitstream.cpp Normal file
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@ -0,0 +1,50 @@
#include "memory_bank_flatten_fabric_bitstream.h"
/* begin namespace openfpga */
namespace openfpga {
size_t MemoryBankFlattenFabricBitstream::size() const {
return bitstream_.size();
}
size_t MemoryBankFlattenFabricBitstream::bl_vector_size() const {
/* The address sizes and data input sizes are the same across any element,
* just get it from the 1st element to save runtime
*/
size_t bl_vec_size = 0;
for (const auto& bl_vec : bitstream_.begin()->second) {
bl_vec_size += bl_vec.size();
}
return bl_vec_size;
}
size_t MemoryBankFlattenFabricBitstream::wl_vector_size() const {
/* The address sizes and data input sizes are the same across any element,
* just get it from the 1st element to save runtime
*/
size_t wl_vec_size = 0;
for (const auto& wl_vec : bitstream_.begin()->first) {
wl_vec_size += wl_vec.size();
}
return wl_vec_size;
}
std::vector<std::string> MemoryBankFlattenFabricBitstream::bl_vector(const std::vector<std::string>& wl_vec) const {
return bitstream_.at(wl_vec);
}
std::vector<std::vector<std::string>> MemoryBankFlattenFabricBitstream::wl_vectors() const {
std::vector<std::vector<std::string>> wl_vecs;
for (const auto& pair : bitstream_) {
wl_vecs.push_back(pair.first);
}
return wl_vecs;
}
void MemoryBankFlattenFabricBitstream::add_blwl_vectors(const std::vector<std::string>& bl_vec,
const std::vector<std::string>& wl_vec) {
/* TODO: Add sanity check. Give a warning if the wl vector is already there */
bitstream_[wl_vec] = bl_vec;
}
} /* end namespace openfpga */

49
openfpga/src/fpga_bitstream/memory_bank_flatten_fabric_bitstream.h Normal file
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@ -0,0 +1,49 @@
#ifndef MEMORY_BANK_FLATTEN_FABRIC_BITSTREAM_H
#define MEMORY_BANK_FLATTEN_FABRIC_BITSTREAM_H
#include <string>
#include <map>
#include <vector>
#include "vtr_vector.h"
/* begin namespace openfpga */
namespace openfpga {
/******************************************************************************
* This files includes data structures that stores a downloadable format of fabric bitstream
* which is compatible with memory bank configuration protocol using flatten BL/WL buses
* @note This data structure is mainly used to output bitstream file for compatible protocols
******************************************************************************/
class MemoryBankFlattenFabricBitstream {
public: /* Accessors */
/* @brief Return the length of bitstream */
size_t size() const;
/* @brief Return the BL address size */
size_t bl_vector_size() const;
/* @brief Return the WL address size */
size_t wl_vector_size() const;
/* @brief Return the BL vectors with a given WL key */
std::vector<std::string> bl_vector(const std::vector<std::string>& wl_vec) const;
/* @brief Return all the WL vectors in a downloaded sequence */
std::vector<std::vector<std::string>> wl_vectors() const;
public: /* Mutators */
/* @brief add a pair of BL/WL vectors to the bitstream database */
void add_blwl_vectors(const std::vector<std::string>& bl_vec,
const std::vector<std::string>& wl_vec);
public: /* Validators */
private: /* Internal data */
/* [(wl_bank0, wl_bank1, ...)] = [(bl_bank0, bl_bank1, ...)]
* Must use (WL, BL) as pairs in the map!!!
* This is because BL data may not be unique while WL must be unique
*/
std::map<std::vector<std::string>, std::vector<std::string>> bitstream_;
};
} /* end namespace openfpga */
#endif

70
openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
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@ -199,14 +199,8 @@ int write_memory_bank_flatten_fabric_bitstream_to_text_file(std::fstream& fp,
/* The address sizes and data input sizes are the same across any element,
* just get it from the 1st element to save runtime
*/
size_t bl_addr_size = 0;
for (const auto& bl_vec : fabric_bits.begin()->second) {
bl_addr_size += bl_vec.size();
}
size_t wl_addr_size = 0;
for (const auto& wl_vec : fabric_bits.begin()->first) {
wl_addr_size += wl_vec.size();
}
size_t bl_addr_size = fabric_bits.bl_vector_size();
size_t wl_addr_size = fabric_bits.wl_vector_size();
/* Output information about how to intepret the bitstream */
fp << "// Bitstream length: " << fabric_bits.size() << std::endl;
@ -215,14 +209,55 @@ int write_memory_bank_flatten_fabric_bitstream_to_text_file(std::fstream& fp,
fp << "<wl_address " << wl_addr_size << " bits>";
fp << std::endl;
for (const auto& addr_pair : fabric_bits) {
for (const auto& wl_vec : fabric_bits.wl_vectors()) {
/* Write BL address code */
for (const auto& bl_vec : addr_pair.second) {
fp << bl_vec;
for (const auto& bl_unit : fabric_bits.bl_vector(wl_vec)) {
fp << bl_unit;
}
/* Write WL address code */
for (const auto& wl_vec : addr_pair.first) {
fp << wl_vec;
for (const auto& wl_unit : wl_vec) {
fp << wl_unit;
}
fp << std::endl;
}
return status;
}
/********************************************************************
* Write the fabric bitstream fitting a memory bank protocol
* to a plain text file
*
* Return:
* - 0 if succeed
* - 1 if critical errors occured
*******************************************************************/
static
int write_memory_bank_shift_register_fabric_bitstream_to_text_file(std::fstream& fp,
const bool& bit_value_to_skip,
const FabricBitstream& fabric_bitstream) {
int status = 0;
MemoryBankFlattenFabricBitstream fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, bit_value_to_skip);
size_t bl_addr_size = fabric_bits.bl_vector_size();
size_t wl_addr_size = fabric_bits.wl_vector_size();
/* Output information about how to intepret the bitstream */
fp << "// Bitstream length: " << fabric_bits.size() << std::endl;
fp << "// Bitstream width (LSB -> MSB): ";
fp << "<bl shift register heads" << bl_addr_size << " bits>";
fp << "<wl shift register heads " << wl_addr_size << " bits>";
fp << std::endl;
for (const auto& wl_vec : fabric_bits.wl_vectors()) {
/* Write BL address code */
for (const auto& bl_unit : fabric_bits.bl_vector(wl_vec)) {
fp << bl_unit;
}
/* Write WL address code */
for (const auto& wl_unit : wl_vec) {
fp << wl_unit;
}
fp << std::endl;
}
@ -369,12 +404,15 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
apply_fast_configuration,
bit_value_to_skip,
fabric_bitstream);
} else {
VTR_ASSERT(BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()
|| BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type());
} else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) {
status = write_memory_bank_flatten_fabric_bitstream_to_text_file(fp,
bit_value_to_skip,
fabric_bitstream);
} else {
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type());
status = write_memory_bank_shift_register_fabric_bitstream_to_text_file(fp,
bit_value_to_skip,
fabric_bitstream);
}
break;
}

2
openfpga/src/utils/fabric_bitstream_utils.cpp
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@ -313,7 +313,7 @@ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(cons
}
}
/* Add the pair to std map */
fabric_bits[cur_wl_vectors] = cur_bl_vectors;
fabric_bits.add_blwl_vectors(cur_bl_vectors, cur_wl_vectors);
}
return fabric_bits;

5
openfpga/src/utils/fabric_bitstream_utils.h
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@ -10,6 +10,7 @@
#include <vector>
#include <map>
#include "bitstream_manager.h"
#include "memory_bank_flatten_fabric_bitstream.h"
#include "fabric_bitstream.h"
/********************************************************************
@ -37,10 +38,6 @@ FrameFabricBitstream build_frame_based_fabric_bitstream_by_address(const FabricB
size_t find_frame_based_fast_configuration_fabric_bitstream_size(const FabricBitstream& fabric_bitstream,
const bool& bit_value_to_skip);
/* Must use (WL, BL) as pairs in the map!!!
* This is because BL data may not be unique while WL must be unique
*/
typedef std::map<std::vector<std::string>, std::vector<std::string>> MemoryBankFlattenFabricBitstream;
/********************************************************************
* @ brief Reorganize the fabric bitstream for memory banks which use flatten or shift register to manipulate BL and WLs
* For each configuration region, we will merge BL address (which are 1-hot codes) under the same WL address