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deploy compact constant values in Verilog codes

This commit is contained in:
tangxifan 2020-05-30 13:04:55 -06:00
parent 0931eccbf6
commit ad7422359d
1 changed files with 1 additions and 1 deletions
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openfpga/src/fpga_verilog/verilog_writer_utils.h
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@ -97,7 +97,7 @@ std::string generate_verilog_local_wire(const BasicPort& output_port,
const std::vector<BasicPort>& input_ports);
std::string generate_verilog_constant_values(const std::vector<size_t>& const_values,
const bool& short_constant = false);
const bool& short_constant = true);
std::string generate_verilog_port_constant_values(const BasicPort& output_port,
const std::vector<size_t>& const_values);