add additional information in the simulation ini file for UVM
This commit is contained in:
tangxifan
parent
e688ca1388
commit
b74dde919d
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@ -14,6 +14,9 @@
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "simulation_utils.h"
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@ -30,6 +33,11 @@ namespace openfpga {
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void print_verilog_simulation_info(const std::string& ini_fname,
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const std::string& circuit_name,
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const std::string& src_dir,
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const AtomContext& atom_ctx,
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const PlacementContext& place_ctx,
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const IoLocationMap& io_location_map,
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const ModuleManager& module_manager,
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const e_config_protocol_type& config_protocol_type,
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const size_t& num_program_clock_cycles,
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const int& num_operating_clock_cycles,
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const float& prog_clock_freq,
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@ -59,6 +67,9 @@ void print_verilog_simulation_info(const std::string& ini_fname,
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1. / prog_clock_freq,
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num_operating_clock_cycles,
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1. / op_clock_freq);
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/* Basic information */
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ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject";
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ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name;
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ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX);
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@ -68,6 +79,58 @@ void print_verilog_simulation_info(const std::string& ini_fname,
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ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME);
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ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX));
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/* Information required by UVM */
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if (CONFIG_MEM_FRAME_BASED == config_protocol_type) {
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/* Find the top_module */
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ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name());
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VTR_ASSERT(true == module_manager.valid_module_id(top_module));
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/* Address port */
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ModulePortId addr_port_id = module_manager.find_module_port(top_module,
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std::string(DECODER_ADDRESS_PORT_NAME));
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BasicPort addr_port = module_manager.module_port(top_module, addr_port_id);
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ini["SIMULATION_DECK"]["ADDR_WIDTH"] = std::to_string(addr_port.get_width());
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/* I/O port */
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std::vector<BasicPort> module_io_ports = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT);
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size_t total_gpio_width = 0;
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for (const BasicPort& module_io_port : module_io_ports) {
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total_gpio_width += module_io_port.get_width();
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}
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ini["SIMULATION_DECK"]["GPIO_WIDTH"] = total_gpio_width;
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/* I/O direction map:
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* - '0' output
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* - '1' input
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* For unused ports, by default we assume it is configured as inputs
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* TODO: this should be reworked to be consistent with bitstream
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*/
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std::string io_direction(total_gpio_width, '1');
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for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
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/* Bypass non-I/O atom blocks ! */
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if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
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&& (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
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continue;
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}
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/* Find the index of the mapped GPIO in top-level FPGA fabric */
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size_t io_index = io_location_map.io_index(place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
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place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.z);
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if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
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io_direction[io_index] = '1';
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} else {
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VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
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io_direction[io_index] = '0';
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}
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}
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/* Organize the vector to string */
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ini["SIMULATION_DECK"]["IO"] = io_direction;
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}
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mINI::INIFile file(ini_fname);
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file.generate(ini, true);
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}
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@ -5,6 +5,10 @@
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <string>
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#include "module_manager.h"
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#include "config_protocol.h"
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#include "vpr_context.h"
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#include "io_location_map.h"
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/********************************************************************
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* Function declaration
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@ -16,6 +20,11 @@ namespace openfpga {
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void print_verilog_simulation_info(const std::string& ini_fname,
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const std::string& circuit_name,
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const std::string& src_dir,
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const AtomContext& atom_ctx,
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const PlacementContext& place_ctx,
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const IoLocationMap& io_location_map,
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const ModuleManager& module_manager,
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const e_config_protocol_type& config_protocol_type,
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const size_t& num_program_clock_cycles,
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const int& num_operating_clock_cycles,
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const float& prog_clock_freq,
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@ -231,6 +231,9 @@ namespace openfpga
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print_verilog_simulation_info(simulation_ini_file_name,
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netlist_name,
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src_dir_path,
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atom_ctx, place_ctx, io_location_map,
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module_manager,
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config_protocol_type,
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bitstream_manager.bits().size(),
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simulation_setting.num_clock_cycles(),
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simulation_setting.programming_clock_frequency(),
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