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OpenFPGA
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add profile time to top module builder for better spot on runtime/memory overhead sources

This commit is contained in:
tangxifan 2020-06-29 23:17:03 -06:00
parent 57e6c84252
commit e7d5736269
4 changed files with 19 additions and 0 deletions
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9
openfpga/src/fabric/build_top_module.cpp
View File

@ -91,6 +91,9 @@ vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
const ModuleId& top_module,
IoLocationMap& io_location_map,
const DeviceGrid& grids) {
vtr::ScopedStartFinishTimer timer("Add grid instances to top module");
/* Reserve an array for the instance ids */
vtr::Matrix<size_t> grid_instance_ids({grids.width(), grids.height()});
grid_instance_ids.fill(size_t(-1));
@ -203,6 +206,9 @@ vtr::Matrix<size_t> add_top_module_switch_block_instances(ModuleManager& module_
const ModuleId& top_module,
const DeviceRRGSB& device_rr_gsb,
const bool& compact_routing_hierarchy) {
vtr::ScopedStartFinishTimer timer("Add switch block instances to top module");
vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
/* Reserve an array for the instance ids */
@ -253,6 +259,9 @@ vtr::Matrix<size_t> add_top_module_connection_block_instances(ModuleManager& mod
const DeviceRRGSB& device_rr_gsb,
const t_rr_type& cb_type,
const bool& compact_routing_hierarchy) {
vtr::ScopedStartFinishTimer timer("Add connection block instances to top module");
vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
/* Reserve an array for the instance ids */

3
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -4,6 +4,7 @@
*******************************************************************/
/* Headers from vtrutil library */
#include "vtr_assert.h"
#include "vtr_time.h"
/* Headers from openfpgautil library */
#include "openfpga_side_manager.h"
@ -648,6 +649,8 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager,
const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin) {
vtr::ScopedStartFinishTimer timer("Add module nets between grids and GSBs");
vtr::Point<size_t> gsb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < gsb_range.x(); ++ix) {

3
openfpga/src/fabric/build_top_module_directs.cpp
View File

@ -8,6 +8,7 @@
/* Headers from vtrutil library */
#include "vtr_assert.h"
#include "vtr_log.h"
#include "vtr_time.h"
/* Headers from openfpgautil library */
#include "openfpga_port.h"
@ -145,6 +146,8 @@ void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager,
const TileDirect& tile_direct,
const ArchDirect& arch_direct) {
vtr::ScopedStartFinishTimer timer("Add module nets for inter-tile connections");
for (const TileDirectId& tile_direct_id : tile_direct.directs()) {
add_module_nets_tile_direct_connection(module_manager, top_module, circuit_lib,
grids, grid_instance_ids,

4
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -7,6 +7,7 @@
/* Headers from vtrutil library */
#include "vtr_assert.h"
#include "vtr_log.h"
#include "vtr_time.h"
/* Headers from vpr library */
#include "vpr_utils.h"
@ -911,6 +912,9 @@ void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_design_tech& mem_tech,
const size_t& num_config_bits) {
vtr::ScopedStartFinishTimer timer("Add module nets for configuration buses");
switch (mem_tech) {
case CIRCUIT_MODEL_DESIGN_CMOS:
add_top_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,