From e7d57362691577e5ce1c31189ace4f59fa871719 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 29 Jun 2020 23:17:03 -0600
Subject: [PATCH] add profile time to top module builder for better spot on
 runtime/memory overhead sources

---
 openfpga/src/fabric/build_top_module.cpp            | 9 +++++++++
 openfpga/src/fabric/build_top_module_connection.cpp | 3 +++
 openfpga/src/fabric/build_top_module_directs.cpp    | 3 +++
 openfpga/src/fabric/build_top_module_memory.cpp     | 4 ++++
 4 files changed, 19 insertions(+)

diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp
index 6c9aa87db..edb25941e 100644
--- a/openfpga/src/fabric/build_top_module.cpp
+++ b/openfpga/src/fabric/build_top_module.cpp
@@ -91,6 +91,9 @@ vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
                                                   const ModuleId& top_module,
                                                   IoLocationMap& io_location_map,
                                                   const DeviceGrid& grids) {
+
+  vtr::ScopedStartFinishTimer timer("Add grid instances to top module");
+
   /* Reserve an array for the instance ids */
   vtr::Matrix<size_t> grid_instance_ids({grids.width(), grids.height()}); 
   grid_instance_ids.fill(size_t(-1));
@@ -203,6 +206,9 @@ vtr::Matrix<size_t> add_top_module_switch_block_instances(ModuleManager& module_
                                                           const ModuleId& top_module, 
                                                           const DeviceRRGSB& device_rr_gsb,
                                                           const bool& compact_routing_hierarchy) {
+
+  vtr::ScopedStartFinishTimer timer("Add switch block instances to top module");
+
   vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
 
   /* Reserve an array for the instance ids */
@@ -253,6 +259,9 @@ vtr::Matrix<size_t> add_top_module_connection_block_instances(ModuleManager& mod
                                                               const DeviceRRGSB& device_rr_gsb,
                                                               const t_rr_type& cb_type,
                                                               const bool& compact_routing_hierarchy) {
+
+  vtr::ScopedStartFinishTimer timer("Add connection block instances to top module");
+
   vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
 
   /* Reserve an array for the instance ids */
diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp
index 629129669..e2cc6c3b2 100644
--- a/openfpga/src/fabric/build_top_module_connection.cpp
+++ b/openfpga/src/fabric/build_top_module_connection.cpp
@@ -4,6 +4,7 @@
  *******************************************************************/
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
+#include "vtr_time.h"
 
 /* Headers from openfpgautil library */
 #include "openfpga_side_manager.h"
@@ -648,6 +649,8 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager,
                                                 const bool& compact_routing_hierarchy,
                                                 const bool& duplicate_grid_pin) {
 
+  vtr::ScopedStartFinishTimer timer("Add module nets between grids and GSBs");
+
   vtr::Point<size_t> gsb_range = device_rr_gsb.get_gsb_range();
 
   for (size_t ix = 0; ix < gsb_range.x(); ++ix) {
diff --git a/openfpga/src/fabric/build_top_module_directs.cpp b/openfpga/src/fabric/build_top_module_directs.cpp
index 81f589adb..1540c3d24 100644
--- a/openfpga/src/fabric/build_top_module_directs.cpp
+++ b/openfpga/src/fabric/build_top_module_directs.cpp
@@ -8,6 +8,7 @@
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
+#include "vtr_time.h"
 
 /* Headers from openfpgautil library */
 #include "openfpga_port.h"
@@ -145,6 +146,8 @@ void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager,
                                                  const TileDirect& tile_direct,
                                                  const ArchDirect& arch_direct) {
 
+  vtr::ScopedStartFinishTimer timer("Add module nets for inter-tile connections");
+
   for (const TileDirectId& tile_direct_id : tile_direct.directs()) {
     add_module_nets_tile_direct_connection(module_manager, top_module, circuit_lib, 
                                            grids, grid_instance_ids,
diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index e37c585d2..219426c79 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -7,6 +7,7 @@
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
+#include "vtr_time.h"
 
 /* Headers from vpr library */
 #include "vpr_utils.h"
@@ -911,6 +912,9 @@ void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
                                            const e_config_protocol_type& sram_orgz_type, 
                                            const e_circuit_model_design_tech& mem_tech,
                                            const size_t& num_config_bits) {
+
+  vtr::ScopedStartFinishTimer timer("Add module nets for configuration buses");
+
   switch (mem_tech) {
   case CIRCUIT_MODEL_DESIGN_CMOS:
     add_top_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,