riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules

This commit is contained in:
tangxifan 2021-09-28 23:27:47 -07:00
parent 7723e00e6c
commit 5da8f1db73
2 changed files with 121 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
openfpga/src/fabric/build_top_module.cpp
View File

@ -341,12 +341,6 @@ int build_top_module(ModuleManager& module_manager,
tile_direct, arch_direct);
}
/* Add global ports to the pb_module:
* This is a much easier job after adding sub modules (instances),
* we just need to find all the global ports from the child modules and build a list of it
*/
add_module_global_ports_from_child_modules(module_manager, top_module);
/* Add global ports from grid ports that are defined as global in tile annotation */
status = add_top_module_global_ports_from_grid_modules(module_manager, top_module, tile_annotation, vpr_device_annotation, grids, grid_instance_ids);
if (CMD_EXEC_FATAL_ERROR == status) {
@ -427,6 +421,13 @@ int build_top_module(ModuleManager& module_manager,
top_module_num_config_bits);
}
/* Add global ports to the top module:
* This is a much easier job after adding sub modules (instances),
* we just need to find all the global ports from the child modules and build a list of it
* @note This function is called after the add_top_module_nets_memory_config_bus() because it may add some sub modules
*/
add_module_global_ports_from_child_modules(module_manager, top_module);
return status;
}

121
openfpga/src/fabric/build_top_module_memory_bank.cpp
View File

@ -912,7 +912,7 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(Module
unique_sr_sizes.push_back(num_bls);
}
/* TODO: Build submodules for shift register chains */
/* Build submodules for shift register chains */
for (const size_t& sr_size : unique_sr_sizes) {
std::string sr_module_name = generate_bl_shift_register_module_name(circuit_lib.model_name(bl_memory_model), sr_size);
ModuleId sr_bank_module = build_bl_shift_register_chain_module(module_manager,
@ -920,12 +920,65 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(Module
sr_module_name,
bl_memory_model,
sr_size);
/* Instanciate the shift register chains in the top-level module */
module_manager.add_child_module(top_module, sr_bank_module);
}
/* TODO: Instanciate the shift register chains in the top-level module */
//module_manager.add_child_module(top_module, sr_bank_module);
/* TODO: create connections between top-level module and the BL shift register banks
* - Connect the head port from top-level module to each shift register bank
* - Connect the tail port from each shift register bank to top-level module
*/
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
ModulePortId blsr_head_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(BL_SHIFT_REGISTER_CHAIN_HEAD_NAME), config_region));
BasicPort blsr_head_port_info = module_manager.module_port(top_module, blsr_head_port);
/* TODO: create connections between top-level module and the BL shift register banks */
for (const size_t& sr_size : unique_sr_sizes) {
std::string sr_module_name = generate_bl_shift_register_module_name(circuit_lib.model_name(bl_memory_model), sr_size);
ModuleId child_sr_module = module_manager.find_module(sr_module_name);
ModulePortId child_blsr_head_port = module_manager.find_module_port(child_sr_module, std::string(BL_SHIFT_REGISTER_CHAIN_HEAD_NAME));
BasicPort child_blsr_head_port_info = module_manager.module_port(child_sr_module, child_blsr_head_port);
for (size_t child_instance = 0; child_instance < module_manager.num_instance(top_module, child_sr_module); ++child_instance) {
for (const size_t& sink_pin : child_blsr_head_port_info.pins()) {
/* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
top_module, 0,
blsr_head_port,
blsr_head_port_info.pins()[sink_pin]);
VTR_ASSERT(ModuleNetId::INVALID() != net);
/* Add net sink */
module_manager.add_module_net_sink(top_module, net,
child_sr_module, child_instance, child_blsr_head_port, sink_pin);
}
}
}
}
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
ModulePortId blsr_tail_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(BL_SHIFT_REGISTER_CHAIN_TAIL_NAME), config_region));
BasicPort blsr_tail_port_info = module_manager.module_port(top_module, blsr_tail_port);
for (const size_t& sr_size : unique_sr_sizes) {
std::string sr_module_name = generate_bl_shift_register_module_name(circuit_lib.model_name(bl_memory_model), sr_size);
ModuleId child_sr_module = module_manager.find_module(sr_module_name);
ModulePortId child_blsr_tail_port = module_manager.find_module_port(child_sr_module, std::string(BL_SHIFT_REGISTER_CHAIN_TAIL_NAME));
BasicPort child_blsr_tail_port_info = module_manager.module_port(child_sr_module, child_blsr_tail_port);
for (size_t child_instance = 0; child_instance < module_manager.num_instance(top_module, child_sr_module); ++child_instance) {
for (const size_t& sink_pin : child_blsr_tail_port_info.pins()) {
/* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
child_sr_module, child_instance,
child_blsr_tail_port, sink_pin);
VTR_ASSERT(ModuleNetId::INVALID() != net);
/* Add net sink */
module_manager.add_module_net_sink(top_module, net,
top_module, 0,
blsr_tail_port, blsr_tail_port_info.pins()[sink_pin]);
}
}
}
}
/* Create connections between BLs of top-level module and BLs of child modules for each region */
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
@ -1134,12 +1187,66 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module
sr_module_name,
wl_memory_model,
sr_size);
/* Instanciate the shift register chains in the top-level module */
module_manager.add_child_module(top_module, sr_bank_module);
}
/* TODO: Instanciate the shift register chains in the top-level module */
//module_manager.add_child_module(top_module, sr_bank_module);
/* TODO: create connections between top-level module and the WL shift register banks
* - Connect the head port from top-level module to each shift register bank
* - Connect the tail port from each shift register bank to top-level module
*/
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
ModulePortId wlsr_head_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(WL_SHIFT_REGISTER_CHAIN_HEAD_NAME), config_region));
BasicPort wlsr_head_port_info = module_manager.module_port(top_module, wlsr_head_port);
for (const size_t& sr_size : unique_sr_sizes) {
std::string sr_module_name = generate_bl_shift_register_module_name(circuit_lib.model_name(wl_memory_model), sr_size);
ModuleId child_sr_module = module_manager.find_module(sr_module_name);
ModulePortId child_wlsr_head_port = module_manager.find_module_port(child_sr_module, std::string(WL_SHIFT_REGISTER_CHAIN_HEAD_NAME));
BasicPort child_wlsr_head_port_info = module_manager.module_port(child_sr_module, child_wlsr_head_port);
for (size_t child_instance = 0; child_instance < module_manager.num_instance(top_module, child_sr_module); ++child_instance) {
for (const size_t& sink_pin : child_wlsr_head_port_info.pins()) {
/* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
top_module, 0,
wlsr_head_port,
wlsr_head_port_info.pins()[sink_pin]);
VTR_ASSERT(ModuleNetId::INVALID() != net);
/* Add net sink */
module_manager.add_module_net_sink(top_module, net,
child_sr_module, child_instance, child_wlsr_head_port, sink_pin);
}
}
}
}
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
ModulePortId wlsr_tail_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(WL_SHIFT_REGISTER_CHAIN_TAIL_NAME), config_region));
BasicPort wlsr_tail_port_info = module_manager.module_port(top_module, wlsr_tail_port);
for (const size_t& sr_size : unique_sr_sizes) {
std::string sr_module_name = generate_wl_shift_register_module_name(circuit_lib.model_name(wl_memory_model), sr_size);
ModuleId child_sr_module = module_manager.find_module(sr_module_name);
ModulePortId child_wlsr_tail_port = module_manager.find_module_port(child_sr_module, std::string(WL_SHIFT_REGISTER_CHAIN_TAIL_NAME));
BasicPort child_wlsr_tail_port_info = module_manager.module_port(child_sr_module, child_wlsr_tail_port);
for (size_t child_instance = 0; child_instance < module_manager.num_instance(top_module, child_sr_module); ++child_instance) {
for (const size_t& sink_pin : child_wlsr_tail_port_info.pins()) {
/* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
child_sr_module, child_instance,
child_wlsr_tail_port, sink_pin);
VTR_ASSERT(ModuleNetId::INVALID() != net);
/* Add net sink */
module_manager.add_module_net_sink(top_module, net,
top_module, 0,
wlsr_tail_port, wlsr_tail_port_info.pins()[sink_pin]);
}
}
}
}
/* TODO: create connections between top-level module and the BL shift register banks */
/* Create connections between WLs of top-level module and WLs of child modules for each region */
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {