[Engine] Adding the function that builds a shift register module for BL/WLs
This commit is contained in:
tangxifan
parent
834bdd2b07
commit
7723e00e6c
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@ -822,6 +822,23 @@ std::string generate_regional_blwl_port_name(const std::string& blwl_port_prefix
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return blwl_port_prefix + std::string("_config_region_") + std::to_string(size_t(region_id));
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}
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/*********************************************************************
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* Generate the module name for a shift register chain which configures BLs
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*********************************************************************/
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std::string generate_bl_shift_register_module_name(const std::string& memory_model_name,
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const size_t& shift_register_size) {
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return std::string("bl_shift_register_") + memory_model_name + std::string("_size") + std::to_string(shift_register_size);
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}
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/*********************************************************************
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* Generate the module name for a shift register chain which configures WLs
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*********************************************************************/
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std::string generate_wl_shift_register_module_name(const std::string& memory_model_name,
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const size_t& shift_register_size) {
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return std::string("wl_shift_register_") + memory_model_name + std::string("_size") + std::to_string(shift_register_size);
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}
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/*********************************************************************
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* Generate the port name for the input bus of a routing multiplexer
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* This is very useful in Verilog code generation where the inputs of
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@ -187,6 +187,12 @@ std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib,
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std::string generate_regional_blwl_port_name(const std::string& blwl_port_prefix,
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const ConfigRegionId& region_id);
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std::string generate_bl_shift_register_module_name(const std::string& memory_model_name,
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const size_t& shift_register_size);
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std::string generate_wl_shift_register_module_name(const std::string& memory_model_name,
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const size_t& shift_register_size);
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std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib,
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const CircuitModelId& mux_model,
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const size_t& mux_size,
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@ -78,7 +78,6 @@ void add_module_input_nets_to_mem_modules(ModuleManager& module_manager,
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* pin of output port of the memory module, where W is the size of port
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* 3. It assumes fixed port name for output ports
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********************************************************************/
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static
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std::vector<ModuleNetId> add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager,
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const ModuleId& mem_module,
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const std::string& mem_module_output_name,
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@ -162,7 +161,6 @@ void add_module_output_nets_to_mem_modules(ModuleManager& module_manager,
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* Do not use it to replace the
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* add_module_nets_cmos_memory_chain_config_bus() !!!
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*********************************************************************/
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static
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void add_module_nets_to_cmos_memory_config_chain_module(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const CircuitLibrary& circuit_lib,
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@ -16,6 +16,22 @@
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/* begin namespace openfpga */
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namespace openfpga {
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std::vector<ModuleNetId> add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager,
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const ModuleId& mem_module,
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const std::string& mem_module_output_name,
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const CircuitLibrary& circuit_lib,
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const CircuitPortId& circuit_port,
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const ModuleId& child_module,
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const size_t& child_index,
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const size_t& child_instance);
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void add_module_nets_to_cmos_memory_config_chain_module(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const CircuitLibrary& circuit_lib,
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const CircuitPortId& model_input_port,
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const CircuitPortId& model_output_port);
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void build_memory_modules(ModuleManager& module_manager,
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DecoderLibrary& arch_decoder_lib,
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const MuxLibrary& mux_lib,
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@ -24,6 +24,7 @@
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#include "decoder_library_utils.h"
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#include "module_manager_utils.h"
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#include "memory_bank_utils.h"
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#include "build_memory_modules.h"
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#include "build_decoder_modules.h"
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#include "build_top_module_memory_bank.h"
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@ -44,11 +45,11 @@ namespace openfpga {
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*
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********************************************************************/
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static
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void build_bl_shift_register_chain_module(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const std::string& module_name,
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const CircuitModelId& sram_model,
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const size_t& num_mems) {
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ModuleId build_bl_shift_register_chain_module(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const std::string& module_name,
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const CircuitModelId& sram_model,
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const size_t& num_mems) {
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/* Get the input ports from the SRAM */
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std::vector<CircuitPortId> sram_input_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_INPUT, true);
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@ -102,13 +103,12 @@ void build_bl_shift_register_chain_module(ModuleManager& module_manager,
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module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance);
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/* Build module nets to wire bl outputs of sram modules to BL outputs of memory module */
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for (size_t iport = 0; iport < num_bl_ports; ++iport) {
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CircuitPortId child_module_output_port = sram_bl_ports[iport];
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for (const auto& child_module_output_port : sram_bl_ports) {
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std::string chain_output_port_name = std::string(BL_SHIFT_REGISTER_CHAIN_BL_OUT_NAME);
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std::vector<ModuleNetId> output_nets = add_module_output_nets_to_chain_mem_modules(module_manager, mem_module,
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chan_output_port_name, circuit_lib,
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child_module_output_port,
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sram_mem_module, i, sram_mem_instance);
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add_module_output_nets_to_chain_mem_modules(module_manager, mem_module,
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chain_output_port_name, circuit_lib,
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child_module_output_port,
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sram_mem_module, i, sram_mem_instance);
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}
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}
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@ -116,21 +116,121 @@ void build_bl_shift_register_chain_module(ModuleManager& module_manager,
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add_module_nets_to_cmos_memory_config_chain_module(module_manager, mem_module,
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circuit_lib, sram_input_ports[0], sram_output_ports[0]);
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/* If there is a second input defined,
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* add nets to short wire the 2nd inputs to the first inputs
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/* Add global ports to the pb_module:
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* This is a much easier job after adding sub modules (instances),
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* we just need to find all the global ports from the child modules and build a list of it
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*/
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if (2 == sram_input_ports.size()) {
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add_module_nets_to_cmos_memory_scan_chain_module(module_manager, mem_module,
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circuit_lib, sram_input_ports[1], sram_output_ports[0]);
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add_module_global_ports_from_child_modules(module_manager, mem_module);
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return mem_module;
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}
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/*********************************************************************
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* WL shift register chain module organization
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*
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* +-------+ +-------+ +-------+
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* chain --->| CCFF |--->| CCFF |--->... --->| CCFF |---->chain
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* input&clock | [0] | | [1] | | [N-1] | output
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* +-------+ +-------+ +-------+
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* | | ... | config-memory output
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* v v v
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* +-----------------------------------------+
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* | WL/WLRs of configurable modules |
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*
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********************************************************************/
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static
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ModuleId build_wl_shift_register_chain_module(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const std::string& module_name,
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const CircuitModelId& sram_model,
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const size_t& num_mems) {
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/* Get the input ports from the SRAM */
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std::vector<CircuitPortId> sram_input_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_INPUT, true);
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VTR_ASSERT(1 == sram_input_ports.size());
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/* Get the output ports from the SRAM */
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std::vector<CircuitPortId> sram_output_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
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VTR_ASSERT(1 == sram_output_ports.size());
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/* Get the WL ports from the SRAM */
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std::vector<CircuitPortId> sram_wl_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WL, true);
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VTR_ASSERT(1 == sram_wl_ports.size());
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/* Get the optional WLR ports from the SRAM */
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std::vector<CircuitPortId> sram_wlr_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WLR, true);
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VTR_ASSERT(0 == sram_wlr_ports.size() || 1 == sram_wlr_ports.size());
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/* Create a module and add to the module manager */
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ModuleId mem_module = module_manager.add_module(module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
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/* Label module usage */
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module_manager.set_module_usage(mem_module, ModuleManager::MODULE_CONFIG);
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/* Add an input port, which is the head of configuration chain in the module */
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/* TODO: restriction!!!
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* consider only the first input of the CCFF model as the D port,
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* which will be connected to the head of the chain
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*/
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BasicPort chain_head_port(WL_SHIFT_REGISTER_CHAIN_HEAD_NAME,
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circuit_lib.port_size(sram_input_ports[0]));
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module_manager.add_port(mem_module, chain_head_port, ModuleManager::MODULE_INPUT_PORT);
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/* Add an output port, which is the tail of configuration chain in the module */
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/* TODO: restriction!!!
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* consider only the first output of the CCFF model as the Q port,
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* which will be connected to the tail of the chain
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*/
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BasicPort chain_tail_port(WL_SHIFT_REGISTER_CHAIN_TAIL_NAME,
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circuit_lib.port_size(sram_output_ports[0]));
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module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_OUTPUT_PORT);
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/* Add the output ports to output BL signals */
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BasicPort chain_wl_port(WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME,
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num_mems);
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module_manager.add_port(mem_module, chain_wl_port, ModuleManager::MODULE_OUTPUT_PORT);
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/* Find the sram module in the module manager */
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ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));
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/* Instanciate each submodule */
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for (size_t i = 0; i < num_mems; ++i) {
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size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module);
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module_manager.add_child_module(mem_module, sram_mem_module);
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module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance);
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/* Build module nets to wire wl outputs of sram modules to WL outputs of memory module */
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for (const auto& child_module_output_port : sram_wl_ports) {
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std::string chain_output_port_name = std::string(WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME);
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add_module_output_nets_to_chain_mem_modules(module_manager, mem_module,
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chain_output_port_name, circuit_lib,
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child_module_output_port,
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sram_mem_module, i, sram_mem_instance);
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}
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/* Build module nets to wire wlr outputs of sram modules to WLR outputs of memory module */
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for (const auto& child_module_output_port : sram_wlr_ports) {
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std::string chain_output_port_name = std::string(WL_SHIFT_REGISTER_CHAIN_WLR_OUT_NAME);
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add_module_output_nets_to_chain_mem_modules(module_manager, mem_module,
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chain_output_port_name, circuit_lib,
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child_module_output_port,
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sram_mem_module, i, sram_mem_instance);
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}
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}
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/* Build module nets to wire the configuration chain */
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add_module_nets_to_cmos_memory_config_chain_module(module_manager, mem_module,
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circuit_lib, sram_input_ports[0], sram_output_ports[0]);
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/* Add global ports to the pb_module:
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* This is a much easier job after adding sub modules (instances),
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* we just need to find all the global ports from the child modules and build a list of it
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*/
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add_module_global_ports_from_child_modules(module_manager, mem_module);
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}
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return mem_module;
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}
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/*********************************************************************
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* This function to add nets for quicklogic memory banks
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@ -813,14 +913,14 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(Module
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}
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/* TODO: Build submodules for shift register chains */
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//for (const size_t& sr_size : unique_sr_sizes) {
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// std::string sr_module_name = generate_bl_shift_register_module_name(bl_memory_model, sr_size);
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// ModuleId sr_bank_module = build_bl_shift_register_chain_module(module_manager,
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// circuit_lib,
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// sr_module_name,
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// bl_memory_model,
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// sr_size);
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//}
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for (const size_t& sr_size : unique_sr_sizes) {
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std::string sr_module_name = generate_bl_shift_register_module_name(circuit_lib.model_name(bl_memory_model), sr_size);
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ModuleId sr_bank_module = build_bl_shift_register_chain_module(module_manager,
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circuit_lib,
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sr_module_name,
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bl_memory_model,
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sr_size);
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}
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/* TODO: Instanciate the shift register chains in the top-level module */
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//module_manager.add_child_module(top_module, sr_bank_module);
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@ -1002,6 +1102,136 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_flatten_config_bus(ModuleManager
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}
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}
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/*********************************************************************
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* Top-level function to add nets for quicklogic memory banks using shift registers to control BL/WLs
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*
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* @note this function only adds the WL configuration bus
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*
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* @note see detailed explanation on the bus connection in function add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus()
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**********************************************************************/
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static
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void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(ModuleManager& module_manager,
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const ModuleId& top_module,
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const CircuitLibrary& circuit_lib,
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const ConfigProtocol& config_protocol) {
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CircuitModelId sram_model = config_protocol.memory_model();
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CircuitModelId wl_memory_model = config_protocol.wl_memory_model();
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/* Find out the unique shift register chain sizes */
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std::vector<size_t> unique_sr_sizes;
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for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
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/* TODO: Need to find how to cut the BLs when there are multiple banks for shift registers in a region */
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size_t num_wls = compute_memory_bank_regional_num_wls(module_manager, top_module,
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config_region,
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circuit_lib, sram_model);
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unique_sr_sizes.push_back(num_wls);
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}
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/* TODO: Build submodules for shift register chains */
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for (const size_t& sr_size : unique_sr_sizes) {
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std::string sr_module_name = generate_wl_shift_register_module_name(circuit_lib.model_name(wl_memory_model), sr_size);
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ModuleId sr_bank_module = build_wl_shift_register_chain_module(module_manager,
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circuit_lib,
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sr_module_name,
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wl_memory_model,
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sr_size);
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}
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/* TODO: Instanciate the shift register chains in the top-level module */
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//module_manager.add_child_module(top_module, sr_bank_module);
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/* TODO: create connections between top-level module and the BL shift register banks */
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/* Create connections between WLs of top-level module and WLs of child modules for each region */
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for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
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/**************************************************************
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* Precompute the BLs and WLs distribution across the FPGA fabric
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* The distribution is a matrix which contains the starting index of BL/WL for each column or row
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*/
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std::pair<int, int> child_y_range = compute_memory_bank_regional_configurable_child_y_range(module_manager, top_module, config_region);
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std::map<int, size_t> num_wls_per_tile = compute_memory_bank_regional_wordline_numbers_per_tile(module_manager, top_module,
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config_region,
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circuit_lib, sram_model);
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std::map<int, size_t> wl_start_index_per_tile = compute_memory_bank_regional_blwl_start_index_per_tile(child_y_range, num_wls_per_tile);
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/**************************************************************
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* Add WL nets from top module to each configurable child
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*/
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ModulePortId top_module_wl_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(MEMORY_WL_PORT_NAME), config_region));
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BasicPort top_module_wl_port_info = module_manager.module_port(top_module, top_module_wl_port);
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for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
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ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
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vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id];
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size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id];
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/* Find the WL port */
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ModulePortId child_wl_port = module_manager.find_module_port(child_module, std::string(MEMORY_WL_PORT_NAME));
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BasicPort child_wl_port_info = module_manager.module_port(child_module, child_wl_port);
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size_t cur_wl_index = 0;
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for (const size_t& sink_wl_pin : child_wl_port_info.pins()) {
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size_t wl_pin_id = wl_start_index_per_tile[coord.y()] + cur_wl_index;
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VTR_ASSERT(wl_pin_id < top_module_wl_port_info.pins().size());
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/* Create net */
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ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
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top_module, 0,
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top_module_wl_port,
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top_module_wl_port_info.pins()[wl_pin_id]);
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VTR_ASSERT(ModuleNetId::INVALID() != net);
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/* Add net sink */
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module_manager.add_module_net_sink(top_module, net,
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child_module, child_instance, child_wl_port, sink_wl_pin);
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cur_wl_index++;
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}
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}
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/**************************************************************
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* Optional: Add WLR nets from top module to each configurable child
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*/
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ModulePortId top_module_wlr_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(std::string(MEMORY_WLR_PORT_NAME), config_region));
|
||||
BasicPort top_module_wlr_port_info;
|
||||
if (top_module_wlr_port) {
|
||||
top_module_wlr_port_info = module_manager.module_port(top_module, top_module_wlr_port);
|
||||
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
|
||||
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
|
||||
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id];
|
||||
|
||||
size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id];
|
||||
|
||||
/* Find the WL port */
|
||||
ModulePortId child_wlr_port = module_manager.find_module_port(child_module, std::string(MEMORY_WLR_PORT_NAME));
|
||||
BasicPort child_wlr_port_info = module_manager.module_port(child_module, child_wlr_port);
|
||||
|
||||
size_t cur_wlr_index = 0;
|
||||
|
||||
for (const size_t& sink_wlr_pin : child_wlr_port_info.pins()) {
|
||||
size_t wlr_pin_id = wl_start_index_per_tile[coord.y()] + cur_wlr_index;
|
||||
VTR_ASSERT(wlr_pin_id < top_module_wlr_port_info.pins().size());
|
||||
|
||||
/* Create net */
|
||||
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
|
||||
top_module, 0,
|
||||
top_module_wlr_port,
|
||||
top_module_wlr_port_info.pins()[wlr_pin_id]);
|
||||
VTR_ASSERT(ModuleNetId::INVALID() != net);
|
||||
|
||||
/* Add net sink */
|
||||
module_manager.add_module_net_sink(top_module, net,
|
||||
child_module, child_instance, child_wlr_port, sink_wlr_pin);
|
||||
|
||||
cur_wlr_index++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* Top-level function to add nets for quicklogic memory banks
|
||||
* - Each configuration region has independent memory bank circuitry
|
||||
|
|
@ -1054,7 +1284,7 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma
|
|||
break;
|
||||
}
|
||||
case BLWL_PROTOCOL_SHIFT_REGISTER: {
|
||||
/* TODO */
|
||||
add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(module_manager, top_module, circuit_lib, config_protocol);
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
|
|
|
|||
Loading…
Reference in New Issue