[FPGA-SPICE] add SPICE writer for logic blocks
This commit is contained in:
tangxifan
parent
5e78e91fdf
commit
1dfb3e06cc
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@ -41,6 +41,8 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx,
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openfpga_ctx.mutable_spice_netlists(),
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openfpga_ctx.arch(),
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openfpga_ctx.mux_lib(),
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g_vpr_ctx.device(),
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openfpga_ctx.vpr_device_annotation(),
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openfpga_ctx.device_rr_gsb(),
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options);
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@ -17,6 +17,7 @@
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#include "spice_constants.h"
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#include "spice_submodule.h"
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#include "spice_routing.h"
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#include "spice_grid.h"
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/* Header file for this source file */
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#include "spice_api.h"
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@ -42,6 +43,8 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const Arch& openfpga_arch,
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const MuxLibrary& mux_lib,
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const DeviceContext &device_ctx,
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const VprDeviceAnnotation &device_annotation,
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const DeviceRRGSB &device_rr_gsb,
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const FabricSpiceOption& options) {
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@ -97,6 +100,13 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
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rr_dir_path);
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}
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/* Generate grids */
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print_spice_grids(netlist_manager,
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module_manager,
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device_ctx, device_annotation,
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lb_dir_path,
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options.verbose_output());
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/* Given a brief stats on how many Spice modules have been written to files */
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VTR_LOGV(options.verbose_output(),
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"Written %lu SPICE modules in total\n",
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@ -11,6 +11,8 @@
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#include "module_manager.h"
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#include "openfpga_arch.h"
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#include "mux_library.h"
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#include "vpr_context.h"
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#include "vpr_device_annotation.h"
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#include "device_rr_gsb.h"
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#include "fabric_spice_options.h"
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@ -25,6 +27,8 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const Arch& openfpga_arch,
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const MuxLibrary& mux_lib,
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const DeviceContext &device_ctx,
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const VprDeviceAnnotation &device_annotation,
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const DeviceRRGSB &device_rr_gsb,
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const FabricSpiceOption& options);
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@ -0,0 +1,434 @@
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/********************************************************************
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* This file includes functions to print SPICE subckts for a Grid
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* (CLBs, I/Os, heterogeneous blocks etc.)
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*******************************************************************/
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/* System header files */
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#include <vector>
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#include <fstream>
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/* Headers from vtrutil library */
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#include "vtr_geometry.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from readarch library */
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#include "physical_types.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "openfpga_side_manager.h"
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/* Headers from vpr library */
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#include "vpr_utils.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "openfpga_physical_tile_utils.h"
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#include "pb_type_utils.h"
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#include "circuit_library_utils.h"
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#include "module_manager_utils.h"
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#include "spice_constants.h"
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#include "spice_writer_utils.h"
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#include "spice_subckt_writer.h"
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#include "spice_grid.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Print SPICE subckts of a primitive node in the pb_graph_node graph
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* This generic function can support all the different types of primitive nodes
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* i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders.
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*
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* The SPICE subckt will consist of two parts:
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* 1. Logic module of the primitive node
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* This module performs the logic function of the block
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* 2. Memory module of the primitive node
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* This module stores the configuration bits for the logic module
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* if the logic module is a programmable resource, such as LUT
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*
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* SPICE subckt structure:
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*
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* Primitive block
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* +---------------------------------------+
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* | |
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* | +---------+ +---------+ |
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* in |----->| |--->| |<------|configuration lines
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* | | Logic |... | Memory | |
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* out|<-----| |--->| | |
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* | +---------+ +---------+ |
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* | |
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* +---------------------------------------+
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*
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*******************************************************************/
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static
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void print_spice_primitive_block(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const std::string& subckt_dir,
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t_pb_graph_node* primitive_pb_graph_node,
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const bool& verbose) {
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/* Ensure a valid pb_graph_node */
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if (nullptr == primitive_pb_graph_node) {
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid primitive_pb_graph_node!\n");
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exit(1);
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}
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/* Give a name to the Verilog netlist */
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/* Create the file name for Verilog */
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std::string spice_fname(subckt_dir
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+ generate_logical_tile_netlist_name(std::string(), primitive_pb_graph_node, std::string(SPICE_NETLIST_FILE_POSTFIX))
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);
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VTR_LOG("Writing SPICE netlist '%s' for primitive pb_type '%s' ...",
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spice_fname.c_str(), primitive_pb_graph_node->pb_type->name);
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VTR_LOGV(verbose, "\n");
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/* Create the file stream */
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std::fstream fp;
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fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(spice_fname.c_str(), fp);
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print_spice_file_header(fp, std::string("SPICE subckts for primitive pb_type: " + std::string(primitive_pb_graph_node->pb_type->name)));
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/* Generate the module name for this primitive pb_graph_node*/
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std::string primitive_module_name = generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
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/* Create a module of the primitive LUT and register it to module manager */
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ModuleId primitive_module = module_manager.find_module(primitive_module_name);
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/* Ensure that the module has been created and thus unique! */
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VTR_ASSERT(true == module_manager.valid_module_id(primitive_module));
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VTR_LOGV(verbose,
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"Writing SPICE codes of logical tile primitive block '%s'...",
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module_manager.module_name(primitive_module).c_str());
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/* Write the spice module */
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write_spice_subckt_to_file(fp, module_manager, primitive_module);
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/* Close file handler */
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fp.close();
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/* Add fname to the netlist name list */
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NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
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VTR_ASSERT(NetlistId::INVALID() != nlist_id);
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netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
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VTR_LOGV(verbose, "Done\n");
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}
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/********************************************************************
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* Print SPICE subckts of physical blocks inside a grid (CLB, I/O. etc.)
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* This function will traverse the graph of complex logic block (t_pb_graph_node)
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* in a recursive way, using a Depth First Search (DFS) algorithm.
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* As such, primitive physical blocks (LUTs, FFs, etc.), leaf node of the pb_graph
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* will be printed out first, while the top-level will be printed out in the last
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*
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* Note: this function will print a unique SPICE subckt for each type of
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* t_pb_graph_node, i.e., t_pb_type, in the graph, in order to enable highly
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* hierarchical Verilog organization as well as simplify the Verilog file sizes.
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*
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* Note: DFS is the right way. Do NOT use BFS.
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* DFS can guarantee that all the sub-modules can be registered properly
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* to its parent in module manager
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*******************************************************************/
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static
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void rec_print_spice_logical_tile(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const VprDeviceAnnotation& device_annotation,
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const std::string& subckt_dir,
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t_pb_graph_node* physical_pb_graph_node,
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const bool& verbose) {
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/* Check cur_pb_graph_node*/
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if (nullptr == physical_pb_graph_node) {
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid physical_pb_graph_node\n");
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exit(1);
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}
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/* Get the pb_type definition related to the node */
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t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
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/* Find the mode that physical implementation of a pb_type */
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t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
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/* For non-leaf node in the pb_type graph:
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* Recursively Depth-First Generate all the child pb_type at the level
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*/
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if (false == is_primitive_pb_type(physical_pb_type)) {
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for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
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/* Go recursive to visit the children */
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rec_print_spice_logical_tile(netlist_manager,
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module_manager, device_annotation,
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subckt_dir,
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&(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
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verbose);
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}
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}
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/* For leaf node, a primitive SPICE subckt will be generated.
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* Note that the primitive may be mapped to a standard cell, we force to use
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* explict port mapping. This aims to avoid any port sequence issues!!!
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*/
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if (true == is_primitive_pb_type(physical_pb_type)) {
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print_spice_primitive_block(netlist_manager,
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module_manager,
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subckt_dir,
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physical_pb_graph_node,
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verbose);
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/* Finish for primitive node, return */
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return;
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}
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/* Give a name to the Verilog netlist */
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/* Create the file name for Verilog */
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std::string spice_fname(subckt_dir
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+ generate_logical_tile_netlist_name(std::string(), physical_pb_graph_node, std::string(SPICE_NETLIST_FILE_POSTFIX))
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);
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VTR_LOG("Writing SPICE netlist '%s' for pb_type '%s' ...",
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spice_fname.c_str(), physical_pb_type->name);
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VTR_LOGV(verbose, "\n");
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/* Create the file stream */
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std::fstream fp;
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fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(spice_fname.c_str(), fp);
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print_spice_file_header(fp, std::string("SPICE subckts for pb_type: " + std::string(physical_pb_type->name)));
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/* Generate the name of the SPICE subckt for this pb_type */
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std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
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/* Register the SPICE subckt in module manager */
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ModuleId pb_module = module_manager.find_module(pb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
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VTR_LOGV(verbose,
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"Writing SPICE codes of pb_type '%s'...",
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module_manager.module_name(pb_module).c_str());
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/* Comment lines */
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print_spice_comment(fp, std::string("BEGIN Physical programmable logic block SPICE subckt: " + std::string(physical_pb_type->name)));
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/* Write the spice module */
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write_spice_subckt_to_file(fp, module_manager, pb_module);
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print_spice_comment(fp, std::string("END Physical programmable logic block SPICE subckt: " + std::string(physical_pb_type->name)));
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/* Close file handler */
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fp.close();
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/* Add fname to the netlist name list */
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NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
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VTR_ASSERT(NetlistId::INVALID() != nlist_id);
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netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
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VTR_LOGV(verbose, "Done\n");
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}
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/*****************************************************************************
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* This function will create a Verilog file and print out a Verilog netlist
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* for the logical tile (pb_graph/pb_type)
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*****************************************************************************/
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static
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void print_spice_logical_tile_netlist(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const VprDeviceAnnotation& device_annotation,
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const std::string& subckt_dir,
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t_pb_graph_node* pb_graph_head,
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const bool& verbose) {
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VTR_LOG("Writing Verilog netlists for logic tile '%s' ...",
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pb_graph_head->pb_type->name);
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VTR_LOG("\n");
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/* Print SPICE subckts for all the pb_types/pb_graph_nodes
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* use a Depth-First Search Algorithm to print the sub-modules
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* Note: DFS is the right way. Do NOT use BFS.
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* DFS can guarantee that all the sub-modules can be registered properly
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* to its parent in module manager
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*/
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/* Print SPICE subckts starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */
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rec_print_spice_logical_tile(netlist_manager,
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module_manager,
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device_annotation,
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subckt_dir,
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pb_graph_head,
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verbose);
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VTR_LOG("Done\n");
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VTR_LOG("\n");
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}
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/*****************************************************************************
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* This function will create a Verilog file and print out a Verilog netlist
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* for a type of physical block
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*
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* For IO blocks:
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* The param 'border_side' is required, which is specify which side of fabric
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* the I/O block locates at.
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*****************************************************************************/
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static
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void print_spice_physical_tile_netlist(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const std::string& subckt_dir,
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t_physical_tile_type_ptr phy_block_type,
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const e_side& border_side) {
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/* Check code: if this is an IO block, the border side MUST be valid */
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if (true == is_io_type(phy_block_type)) {
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VTR_ASSERT(NUM_SIDES != border_side);
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}
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/* Give a name to the Verilog netlist */
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/* Create the file name for Verilog */
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std::string spice_fname(subckt_dir
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+ generate_grid_block_netlist_name(std::string(GRID_MODULE_NAME_PREFIX) + std::string(phy_block_type->name),
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is_io_type(phy_block_type),
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border_side,
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std::string(SPICE_NETLIST_FILE_POSTFIX))
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);
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/* Echo status */
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if (true == is_io_type(phy_block_type)) {
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SideManager side_manager(border_side);
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VTR_LOG("Writing SPICE Netlist '%s' for physical tile '%s' at %s side ...",
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spice_fname.c_str(), phy_block_type->name,
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side_manager.c_str());
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} else {
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VTR_LOG("Writing SPICE Netlist '%s' for physical_tile '%s'...",
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spice_fname.c_str(), phy_block_type->name);
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}
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/* Create the file stream */
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std::fstream fp;
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fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(spice_fname.c_str(), fp);
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print_spice_file_header(fp, std::string("SPICE subckts for physical tile: " + std::string(phy_block_type->name) + "]"));
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/* Create a Verilog Module for the top-level physical block, and add to module manager */
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std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_SPICE_FILE_NAME_PREFIX), std::string(phy_block_type->name), is_io_type(phy_block_type), border_side);
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ModuleId grid_module = module_manager.find_module(grid_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
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/* Write the spice module */
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print_spice_comment(fp, std::string("BEGIN Grid SPICE subckt: " + module_manager.module_name(grid_module)));
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write_spice_subckt_to_file(fp, module_manager, grid_module);
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print_spice_comment(fp, std::string("END Grid SPICE subckt: " + module_manager.module_name(grid_module)));
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/* Add an empty line as a splitter */
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fp << std::endl;
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/* Close file handler */
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fp.close();
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/* Add fname to the netlist name list */
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NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
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VTR_ASSERT(NetlistId::INVALID() != nlist_id);
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netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
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VTR_LOG("Done\n");
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}
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/*****************************************************************************
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* Create logic block modules in a compact way:
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* 1. Only one module for each I/O on each border side (IO_TYPE)
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* 2. Only one module for each CLB (FILL_TYPE)
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* 3. Only one module for each heterogeneous block
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****************************************************************************/
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void print_spice_grids(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const DeviceContext& device_ctx,
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const VprDeviceAnnotation& device_annotation,
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const std::string& subckt_dir,
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const bool& verbose) {
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/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
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std::vector<std::string> netlist_names;
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/* Enumerate the types of logical tiles, and build a module for each
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* Write modules for all the pb_types/pb_graph_nodes
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* use a Depth-First Search Algorithm to print the sub-modules
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* Note: DFS is the right way. Do NOT use BFS.
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* DFS can guarantee that all the sub-modules can be registered properly
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* to its parent in module manager
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*/
|
||||
VTR_LOG("Writing logical tiles...");
|
||||
VTR_LOGV(verbose, "\n");
|
||||
for (const t_logical_block_type& logical_tile : device_ctx.logical_block_types) {
|
||||
/* Bypass empty pb_graph */
|
||||
if (nullptr == logical_tile.pb_graph_head) {
|
||||
continue;
|
||||
}
|
||||
print_spice_logical_tile_netlist(netlist_manager,
|
||||
module_manager,
|
||||
device_annotation,
|
||||
subckt_dir,
|
||||
logical_tile.pb_graph_head,
|
||||
verbose);
|
||||
}
|
||||
VTR_LOG("Writing logical tiles...");
|
||||
VTR_LOG("Done\n");
|
||||
|
||||
VTR_LOG("\n");
|
||||
|
||||
/* Enumerate the types of physical tiles
|
||||
* Use the logical tile module to build the physical tiles
|
||||
*/
|
||||
VTR_LOG("Building physical tiles...");
|
||||
VTR_LOGV(verbose, "\n");
|
||||
for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
|
||||
/* Bypass empty type or nullptr */
|
||||
if (true == is_empty_type(&physical_tile)) {
|
||||
continue;
|
||||
} else if (true == is_io_type(&physical_tile)) {
|
||||
/* Special for I/O block:
|
||||
* We will search the grids and see where the I/O blocks are located:
|
||||
* - If a I/O block locates on border sides of FPGA fabric:
|
||||
* i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT},
|
||||
* we will generate one module for each border side
|
||||
* - If a I/O block locates in the center of FPGA fabric:
|
||||
* we will generate one module with NUM_SIDES (same treatment as regular grids)
|
||||
*/
|
||||
std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
|
||||
&physical_tile);
|
||||
for (const e_side& io_type_side : io_type_sides) {
|
||||
print_spice_physical_tile_netlist(netlist_manager,
|
||||
module_manager,
|
||||
subckt_dir,
|
||||
&physical_tile,
|
||||
io_type_side);
|
||||
}
|
||||
continue;
|
||||
} else {
|
||||
/* For CLB and heterogenenous blocks */
|
||||
print_spice_physical_tile_netlist(netlist_manager,
|
||||
module_manager,
|
||||
subckt_dir,
|
||||
&physical_tile,
|
||||
NUM_SIDES);
|
||||
}
|
||||
}
|
||||
VTR_LOG("Building physical tiles...");
|
||||
VTR_LOG("Done\n");
|
||||
VTR_LOG("\n");
|
||||
|
||||
/* Output a header file for all the logic blocks */
|
||||
/*
|
||||
std::string grid_spice_fname(LOGIC_BLOCK_VERILOG_FILE_NAME);
|
||||
VTR_LOG("Writing header file for grid SPICE subckts '%s' ...",
|
||||
grid_spice_fname.c_str());
|
||||
print_spice_netlist_include_header_file(netlist_names,
|
||||
subckt_dir.c_str(),
|
||||
grid_spice_fname.c_str());
|
||||
VTR_LOG("Done\n");
|
||||
*/
|
||||
}
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
#ifndef SPICE_GRID_H
|
||||
#define SPICE_GRID_H
|
||||
|
||||
/********************************************************************
|
||||
* Include header files that are required by function declaration
|
||||
*******************************************************************/
|
||||
#include <string>
|
||||
#include "vpr_context.h"
|
||||
#include "module_manager.h"
|
||||
#include "netlist_manager.h"
|
||||
#include "vpr_device_annotation.h"
|
||||
|
||||
/********************************************************************
|
||||
* Function declaration
|
||||
*******************************************************************/
|
||||
|
||||
/* begin namespace openfpga */
|
||||
namespace openfpga {
|
||||
|
||||
void print_spice_grids(NetlistManager& netlist_manager,
|
||||
const ModuleManager& module_manager,
|
||||
const DeviceContext& device_ctx,
|
||||
const VprDeviceAnnotation& device_annotation,
|
||||
const std::string& subckt_dir,
|
||||
const bool& verbose);
|
||||
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue