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[Tool] Rework pin constarint API to avoid expose raw data to judge for developers

This commit is contained in:
tangxifan 2021-04-18 12:02:49 -06:00
parent 6e9b24f9bf
commit 6550ea3dfa
4 changed files with 29 additions and 7 deletions
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8
libopenfpga/libpcf/src/pin_constraints.cpp
View File

@ -81,3 +81,11 @@ PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort&
bool PinConstraints::valid_pin_constraint_id(const PinConstraintId& pin_constraint_id) const {
return ( size_t(pin_constraint_id) < pin_constraint_ids_.size() ) && ( pin_constraint_id == pin_constraint_ids_[pin_constraint_id] );
}
bool PinConstraints::unconstrained_net(const std::string& net) const {
return net.empty();
}
bool PinConstraints::unmapped_net(const std::string& net) const {
return std::string(PIN_CONSTRAINT_OPEN_NET) == net;
}

16
libopenfpga/libpcf/src/pin_constraints.h
View File

@ -61,7 +61,6 @@ class PinConstraints {
bool empty() const;
public: /* Public Mutators */
/* Reserve a number of design constraints to be memory efficent */
void reserve_pin_constraints(const size_t& num_pin_constraints);
@ -70,7 +69,22 @@ class PinConstraints {
const std::string& net);
public: /* Public invalidators/validators */
/* Show if the pin constraint id is a valid for data queries */
bool valid_pin_constraint_id(const PinConstraintId& pin_constraint_id) const;
/* Show if the net has no constraints (free to map to any pin)
* This function is used to identify the net name returned by APIs:
* - pin_net()
* - net()
*/
bool unconstrained_net(const std::string& net) const;
/* Show if the net is defined specifically not to map to any pin
* This function is used to identify the net name returned by APIs:
* - pin_net()
* - net()
*/
bool unmapped_net(const std::string& net) const;
private: /* Internal data */
/* Unique ids for each design constraint */
vtr::vector<PinConstraintId, PinConstraintId> pin_constraint_ids_;

8
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -138,7 +138,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
std::string constrained_net_name = pin_constraints.pin_net(module_clock_pin);
/* If constrained to an open net or there is no clock in the benchmark, we assign it to a default value */
if ( (std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name)
if ( (true == pin_constraints.unmapped_net(constrained_net_name))
|| (true == benchmark_clock_port_names.empty())) {
std::vector<size_t> default_values(1, fabric_global_ports.global_port_default_value(global_port_id));
print_verilog_wire_constant_values(fp, module_clock_pin, default_values);
@ -146,7 +146,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
}
std::string clock_name_to_connect;
if (!constrained_net_name.empty()) {
if (!pin_constraints.unconstrained_net(constrained_net_name)) {
clock_name_to_connect = constrained_net_name;
} else {
/* Otherwise, we must have a clear one-to-one clock net corresponding!!! */
@ -178,8 +178,8 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
/* - If constrained to a given net in the benchmark, we connect the global pin to the net
* - If constrained to an open net in the benchmark, we assign it to a default value
*/
if ( (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name)
&& (!constrained_net_name.empty())) {
if ( (false == pin_constraints.unconstrained_net(constrained_net_name))
&& (false == pin_constraints.unmapped_net(constrained_net_name))) {
BasicPort benchmark_pin(constrained_net_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 1);
print_verilog_wire_connection(fp, module_global_pin, benchmark_pin, false);
} else {

4
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -409,8 +409,8 @@ void print_verilog_top_testbench_global_reset_ports_stimuli(std::fstream& fp,
std::string constrained_net_name = pin_constraints.pin_net(module_global_pin);
/* - If constrained to a given net in the benchmark, we connect the global pin to the net */
if ( (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name)
&& (!constrained_net_name.empty())) {
if ( (false == pin_constraints.unconstrained_net(constrained_net_name))
&& (false == pin_constraints.unmapped_net(constrained_net_name))) {
BasicPort benchmark_pin(constrained_net_name, 1);
print_verilog_wire_connection(fp, module_global_pin,
benchmark_pin,