use efficient net builder in top module connection builder
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@ -14,6 +14,7 @@
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#include "pb_type_utils.h"
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#include "rr_gsb_utils.h"
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#include "openfpga_physical_tile_utils.h"
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#include "module_manager_utils.h"
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#include "build_top_module_utils.h"
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#include "build_top_module_connection.h"
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@ -129,9 +130,7 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) {
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ModuleNetId net = module_manager.create_module_net(top_module);
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/* Configure the net source */
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module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]);
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ModuleNetId net = create_module_source_pin_net(module_manager, top_module, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]);
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/* Configure the net sink */
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module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]);
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}
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@ -274,9 +273,7 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) {
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ModuleNetId net = module_manager.create_module_net(top_module);
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/* Configure the net source */
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module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]);
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ModuleNetId net = create_module_source_pin_net(module_manager, top_module, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]);
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/* Configure the net sink */
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module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]);
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}
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@ -424,9 +421,7 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager,
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); ++pin_id) {
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ModuleNetId net = module_manager.create_module_net(top_module);
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/* Configure the net source */
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module_manager.add_module_net_source(top_module, net, src_cb_module, src_cb_instance, src_cb_port_id, src_cb_port.pins()[pin_id]);
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ModuleNetId net = create_module_source_pin_net(module_manager, top_module, src_cb_module, src_cb_instance, src_cb_port_id, src_cb_port.pins()[pin_id]);
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/* Configure the net sink */
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module_manager.add_module_net_sink(top_module, net, sink_grid_module, sink_grid_instance, sink_grid_port_id, sink_grid_port.pins()[pin_id]);
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}
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@ -587,17 +582,16 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager,
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < cb_port.pins().size(); ++pin_id) {
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ModuleNetId net = module_manager.create_module_net(top_module);
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/* Configure the net source and sink:
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* If sb port is an output (source), cb port is an input (sink)
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* If sb port is an input (sink), cb port is an output (source)
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*/
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if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) {
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ModuleNetId net = create_module_source_pin_net(module_manager, top_module, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]);
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module_manager.add_module_net_sink(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]);
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module_manager.add_module_net_source(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]);
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} else {
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VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack));
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module_manager.add_module_net_source(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]);
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ModuleNetId net = create_module_source_pin_net(module_manager, top_module, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]);
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module_manager.add_module_net_sink(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]);
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}
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}
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