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[Tool] Now users can specify a different fabric netlist when generating Verilog testbench

This commit is contained in:
tangxifan 2020-10-12 12:31:51 -06:00
parent ccaa697e5a
commit 1ef0898f41
7 changed files with 30 additions and 1 deletions
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2
openfpga/src/base/openfpga_verilog.cpp
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@ -65,6 +65,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench");
CommandOptionId opt_fast_configuration = cmd.option("fast_configuration");
@ -79,6 +80,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
*/
VerilogTestbenchOption options;
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist));
options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench));

4
openfpga/src/base/openfpga_verilog_command.cpp
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@ -72,6 +72,10 @@ ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell<Open
shell_cmd.set_option_short_name(output_opt, "f");
shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
/* Add an option '--fabric_netlist_file_path'*/
CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "Specify the file path to the fabric Verilog netlist");
shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING);
/* Add an option '--reference_benchmark_file_path'*/
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);

1
openfpga/src/fpga_verilog/verilog_api.cpp
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@ -235,6 +235,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
}

8
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
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@ -96,6 +96,7 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
*******************************************************************/
void print_verilog_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
@ -116,7 +117,12 @@ void print_verilog_testbench_include_netlists(const std::string& src_dir,
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME));
if (true == fabric_netlist_file.empty()) {
print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME));
} else {
VTR_ASSERT_SAFE(false == fabric_netlist_file.empty());
print_verilog_include_netlist(fp, fabric_netlist_file);
}
fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */

1
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
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@ -23,6 +23,7 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
void print_verilog_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file);
void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,

9
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
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@ -14,6 +14,7 @@ namespace openfpga {
*************************************************/
VerilogTestbenchOption::VerilogTestbenchOption() {
output_directory_.clear();
fabric_netlist_file_path_.clear();
reference_benchmark_file_path_.clear();
print_preconfig_top_testbench_ = false;
print_formal_verification_top_netlist_ = false;
@ -30,6 +31,10 @@ std::string VerilogTestbenchOption::output_directory() const {
return output_directory_;
}
std::string VerilogTestbenchOption::fabric_netlist_file_path() const {
return fabric_netlist_file_path_;
}
std::string VerilogTestbenchOption::reference_benchmark_file_path() const {
return reference_benchmark_file_path_;
}
@ -73,6 +78,10 @@ void VerilogTestbenchOption::set_output_directory(const std::string& output_dir)
output_directory_ = output_dir;
}
void VerilogTestbenchOption::set_fabric_netlist_file_path(const std::string& fabric_netlist_file_path) {
fabric_netlist_file_path_ = fabric_netlist_file_path;
}
void VerilogTestbenchOption::set_reference_benchmark_file_path(const std::string& reference_benchmark_file_path) {
reference_benchmark_file_path_ = reference_benchmark_file_path;
/* Chain effect on other options:

6
openfpga/src/fpga_verilog/verilog_testbench_options.h
View File

@ -23,6 +23,7 @@ class VerilogTestbenchOption {
VerilogTestbenchOption();
public: /* Public accessors */
std::string output_directory() const;
std::string fabric_netlist_file_path() const;
std::string reference_benchmark_file_path() const;
bool fast_configuration() const;
bool print_formal_verification_top_netlist() const;
@ -42,6 +43,10 @@ class VerilogTestbenchOption {
* If the file path is empty, the above testbench generation will not be enabled
*/
void set_reference_benchmark_file_path(const std::string& reference_benchmark_file_path);
/* The fabric netlist file path is an optional parameter
* to allow users to specify a fabric netlist at another location
*/
void set_fabric_netlist_file_path(const std::string& fabric_netlist_file_path);
void set_print_formal_verification_top_netlist(const bool& enabled);
/* The preconfig top testbench generation can be enabled only when formal verification top netlist is enabled */
void set_print_preconfig_top_testbench(const bool& enabled);
@ -52,6 +57,7 @@ class VerilogTestbenchOption {
void set_verbose_output(const bool& enabled);
private: /* Internal Data */
std::string output_directory_;
std::string fabric_netlist_file_path_;
std::string reference_benchmark_file_path_;
bool fast_configuration_;
bool print_formal_verification_top_netlist_;