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use fast method to inquire number of bits and blocks in bitstream databases

This commit is contained in:
tangxifan 2020-07-03 10:55:25 -06:00
parent 6397cbe9d2
commit 6ea857ae6c
9 changed files with 28 additions and 13 deletions
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8
libopenfpga/libfpgabitstream/src/bitstream_manager.cpp
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@ -23,11 +23,19 @@ BitstreamManager::BitstreamManager() {
* Public Accessors : Aggregates
*************************************************/
/* Find all the configuration bits */
size_t BitstreamManager::num_bits() const {
return num_bits_;
}
BitstreamManager::config_bit_range BitstreamManager::bits() const {
return vtr::make_range(config_bit_iterator(ConfigBitId(0), invalid_bit_ids_),
config_bit_iterator(ConfigBitId(num_bits_), invalid_bit_ids_));
}
size_t BitstreamManager::num_blocks() const {
return num_blocks_;
}
/* Find all the configuration blocks */
BitstreamManager::config_block_range BitstreamManager::blocks() const {
return vtr::make_range(config_block_iterator(ConfigBlockId(0), invalid_block_ids_),

2
libopenfpga/libfpgabitstream/src/bitstream_manager.h
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@ -109,8 +109,10 @@ class BitstreamManager {
public: /* Public aggregators */
/* Find all the configuration bits */
size_t num_bits() const;
config_bit_range bits() const;
size_t num_blocks() const;
config_block_range blocks() const;
public: /* Public Accessors */

8
openfpga/src/fpga_bitstream/build_device_bitstream.cpp
View File

@ -173,11 +173,11 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
VTR_LOGV(verbose,
"Decoded %lu configuration bits into %lu blocks\n",
bitstream_manager.bits().size(),
bitstream_manager.blocks().size());
bitstream_manager.num_bits(),
bitstream_manager.num_blocks());
//VTR_ASSERT(num_blocks_to_reserve == bitstream_manager.blocks().size());
//VTR_ASSERT(num_bits_to_reserve == bitstream_manager.bits().size());
//VTR_ASSERT(num_blocks_to_reserve == bitstream_manager.num_blocks());
//VTR_ASSERT(num_bits_to_reserve == bitstream_manager.num_bits());
return bitstream_manager;
}

12
openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
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@ -380,7 +380,7 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
switch (config_protocol.type()) {
case CONFIG_MEM_STANDALONE: {
/* Reserve bits before build-up */
fabric_bitstream.reserve_bits(bitstream_manager.bits().size());
fabric_bitstream.reserve_bits(bitstream_manager.num_bits());
rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, top_block,
module_manager, top_module,
@ -389,7 +389,7 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
}
case CONFIG_MEM_SCAN_CHAIN: {
/* Reserve bits before build-up */
fabric_bitstream.reserve_bits(bitstream_manager.bits().size());
fabric_bitstream.reserve_bits(bitstream_manager.num_bits());
rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, top_block,
module_manager, top_module,
@ -401,7 +401,7 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
/* Reserve bits before build-up */
fabric_bitstream.set_use_address(true);
fabric_bitstream.set_use_wl_address(true);
fabric_bitstream.reserve_bits(bitstream_manager.bits().size());
fabric_bitstream.reserve_bits(bitstream_manager.num_bits());
size_t cur_mem_index = 0;
/* Find BL address port size */
@ -438,7 +438,7 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
case CONFIG_MEM_FRAME_BASED: {
/* Reserve bits before build-up */
fabric_bitstream.set_use_address(true);
fabric_bitstream.reserve_bits(bitstream_manager.bits().size());
fabric_bitstream.reserve_bits(bitstream_manager.num_bits());
rec_build_module_fabric_dependent_frame_bitstream(bitstream_manager,
std::vector<ConfigBlockId>(1, top_block),
@ -474,7 +474,7 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
*/
/* Ensure our fabric bitstream is in the same size as device bistream */
VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.bits().size());
VTR_ASSERT(bitstream_manager.num_bits() == fabric_bitstream.num_bits());
}
/********************************************************************
@ -518,7 +518,7 @@ FabricBitstream build_fabric_dependent_bitstream(const BitstreamManager& bitstre
VTR_LOGV(verbose,
"Built %lu configuration bits for fabric\n",
fabric_bitstream.bits().size());
fabric_bitstream.num_bits());
return fabric_bitstream;
}

4
openfpga/src/fpga_bitstream/fabric_bitstream.cpp
View File

@ -20,6 +20,10 @@ FabricBitstream::FabricBitstream() {
/**************************************************
* Public Accessors : Aggregates
*************************************************/
size_t FabricBitstream::num_bits() const {
return num_bits_;
}
/* Find all the configuration bits */
FabricBitstream::fabric_bit_range FabricBitstream::bits() const {
return vtr::make_range(fabric_bit_iterator(FabricBitId(0), invalid_bit_ids_),

1
openfpga/src/fpga_bitstream/fabric_bitstream.h
View File

@ -101,6 +101,7 @@ class FabricBitstream {
public: /* Public aggregators */
/* Find all the configuration bits */
size_t num_bits() const;
fabric_bit_range bits() const;
public: /* Public Accessors */

2
openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp
View File

@ -101,7 +101,7 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n");
}
std::string timer_message = std::string("Write ") + std::to_string(fabric_bitstream.bits().size()) + std::string(" fabric bitstream into plain text file '") + fname + std::string("'");
std::string timer_message = std::string("Write ") + std::to_string(fabric_bitstream.num_bits()) + std::string(" fabric bitstream into plain text file '") + fname + std::string("'");
vtr::ScopedStartFinishTimer timer(timer_message);
/* Create the file stream */

2
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -234,7 +234,7 @@ namespace openfpga
atom_ctx, place_ctx, io_location_map,
module_manager,
config_protocol_type,
bitstream_manager.bits().size(),
bitstream_manager.num_bits(),
simulation_setting.num_clock_cycles(),
simulation_setting.programming_clock_frequency(),
simulation_setting.operating_clock_frequency());

2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -562,7 +562,7 @@ static
size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz_type,
const bool& fast_configuration,
const FabricBitstream& fabric_bitstream) {
size_t num_config_clock_cycles = 1 + fabric_bitstream.bits().size();
size_t num_config_clock_cycles = 1 + fabric_bitstream.num_bits();
/* Branch on the type of configuration protocol */
switch (sram_orgz_type) {