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[Tool] Bug fix for redundant endif in netlists

This commit is contained in:
tangxifan 2021-06-29 17:02:16 -06:00
parent b83eef47b4
commit b5df1f9aeb
1 changed files with 0 additions and 4 deletions
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4
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
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@ -123,9 +123,7 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
/* Include reference benchmark netlist only when auto-check flag is enabled */
if (!no_self_checking) {
fp << "\t";
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
print_verilog_endif(fp);
fp << std::endl;
}
@ -171,9 +169,7 @@ void print_verilog_preconfigured_testbench_include_netlists(const std::string& s
/* Include reference benchmark netlist only when auto-check flag is enabled */
if (!no_self_checking) {
fp << "\t";
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
print_verilog_endif(fp);
fp << std::endl;
}