use encoded address in storage of fabric bitstream to save memory

libopenfpga/libopenfpgautil/src/openfpga_decode.cpp

@@ -103,4 +103,29 @@ std::vector<char> itobin_charvec(const size_t& in_int,
   return ret;
 }
 
+/******************************************************************** 
+ * Converter a binary vector to an integer
+ * For example: 
+ *   Binary length : 3
+ *   Input:
+ *     index | 0 | 1 | 2
+ *     ret   | 0 | 0 | 1 
+ *
+ *   Output integer: 4
+ *
+ * This function is optimized to return a vector of char
+ * which has a smaller memory footprint than size_t
+ ********************************************************************/
+size_t bintoi_charvec(const std::vector<char>& bin) {
+  size_t ret = 0;
+
+  for (size_t i = 0; i < bin.size(); ++i) {
+    if ('1' == bin[i]) {
+      ret += pow(2., i);
+    }
+  }
+
+  return ret;
+}
+
 } /* end namespace openfpga */

libopenfpga/libopenfpgautil/src/openfpga_decode.h

@@ -21,6 +21,8 @@ std::vector<size_t> itobin_vec(const size_t& in_int,
 std::vector<char> itobin_charvec(const size_t& in_int,
                                  const size_t& bin_len);
 
+size_t bintoi_charvec(const std::vector<char>& bin);
+
 } /* namespace openfpga ends */
 
 #endif

openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp

@@ -398,10 +398,6 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
     break;
   }
   case CONFIG_MEM_MEMORY_BANK: { 
-    /* Reserve bits before build-up */
-    fabric_bitstream.set_use_address(true);
-    fabric_bitstream.set_use_wl_address(true);
-    fabric_bitstream.reserve_bits(bitstream_manager.num_bits());
 
     size_t cur_mem_index = 0;
     /* Find BL address port size */
@@ -426,6 +422,13 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
     ModulePortId wl_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
     BasicPort wl_port_info = module_manager.module_port(wl_decoder_module, wl_port);
 
+    /* Reserve bits before build-up */
+    fabric_bitstream.set_use_address(true);
+    fabric_bitstream.set_use_wl_address(true);
+    fabric_bitstream.set_bl_address_length(bl_port_info.get_width());
+    fabric_bitstream.set_wl_address_length(wl_port_info.get_width());
+    fabric_bitstream.reserve_bits(bitstream_manager.num_bits());
+
     rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, top_block,
                                                             module_manager, top_module, top_module, 
                                                             bl_addr_port_info.get_width(),
@@ -436,9 +439,15 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
     break;
   }
   case CONFIG_MEM_FRAME_BASED: {
+
+    /* Find address port size */
+    ModulePortId addr_port = module_manager.find_module_port(top_module, std::string(DECODER_ADDRESS_PORT_NAME));
+    BasicPort addr_port_info = module_manager.module_port(top_module, addr_port);
+
     /* Reserve bits before build-up */
     fabric_bitstream.set_use_address(true);
     fabric_bitstream.reserve_bits(bitstream_manager.num_bits());
+    fabric_bitstream.set_address_length(addr_port_info.get_width());
 
     rec_build_module_fabric_dependent_frame_bitstream(bitstream_manager,
                                                       std::vector<ConfigBlockId>(1, top_block),

openfpga/src/fpga_bitstream/fabric_bitstream.cpp

@@ -4,6 +4,7 @@
 #include <algorithm>
 
 #include "vtr_assert.h"
+#include "openfpga_decode.h"
 #include "fabric_bitstream.h"
 
 /* begin namespace openfpga */
@@ -15,6 +16,8 @@ namespace openfpga {
 FabricBitstream::FabricBitstream() {
   num_bits_ = 0;
   invalid_bit_ids_.clear();
+  address_length_ = 0;
+  wl_address_length_ = 0;
 }
 
 /**************************************************
@@ -45,7 +48,7 @@ std::vector<char> FabricBitstream::bit_address(const FabricBitId& bit_id) const
   VTR_ASSERT(true == valid_bit_id(bit_id));
   VTR_ASSERT(true == use_address_);
 
-  return bit_addresses_[bit_id];
+  return itobin_charvec(bit_addresses_[bit_id], address_length_);
 }
 
 std::vector<char> FabricBitstream::bit_bl_address(const FabricBitId& bit_id) const {
@@ -58,7 +61,7 @@ std::vector<char> FabricBitstream::bit_wl_address(const FabricBitId& bit_id) con
   VTR_ASSERT(true == use_address_);
   VTR_ASSERT(true == use_wl_address_);
 
-  return bit_wl_addresses_[bit_id];
+  return itobin_charvec(bit_wl_addresses_[bit_id], wl_address_length_);
 }
 
 char FabricBitstream::bit_din(const FabricBitId& bit_id) const {
@@ -106,7 +109,8 @@ void FabricBitstream::set_bit_address(const FabricBitId& bit_id,
                                       const std::vector<char>& address) {
   VTR_ASSERT(true == valid_bit_id(bit_id));
   VTR_ASSERT(true == use_address_);
-  bit_addresses_[bit_id] = address;
+  VTR_ASSERT(address_length_ == address.size());
+  bit_addresses_[bit_id] = bintoi_charvec(address);
 }
 
 void FabricBitstream::set_bit_bl_address(const FabricBitId& bit_id,
@@ -119,7 +123,8 @@ void FabricBitstream::set_bit_wl_address(const FabricBitId& bit_id,
   VTR_ASSERT(true == valid_bit_id(bit_id));
   VTR_ASSERT(true == use_address_);
   VTR_ASSERT(true == use_wl_address_);
-  bit_wl_addresses_[bit_id] = address;
+  VTR_ASSERT(wl_address_length_ == address.size());
+  bit_wl_addresses_[bit_id] = bintoi_charvec(address);
 }
 
 void FabricBitstream::set_bit_din(const FabricBitId& bit_id,
@@ -149,6 +154,16 @@ void FabricBitstream::set_use_address(const bool& enable) {
   }
 }
 
+void FabricBitstream::set_address_length(const size_t& length) {
+  if (true == use_address_) {
+    address_length_ = length; 
+  }
+}
+
+void FabricBitstream::set_bl_address_length(const size_t& length) {
+  set_address_length(length);
+}
+
 void FabricBitstream::set_use_wl_address(const bool& enable) {
   /* Add a lock, only can be modified when num bits are zero*/
   if (0 == num_bits_) {
@@ -156,6 +171,12 @@ void FabricBitstream::set_use_wl_address(const bool& enable) {
   }
 }
 
+void FabricBitstream::set_wl_address_length(const size_t& length) {
+  if (true == use_address_) {
+    wl_address_length_ = length; 
+  }
+}
+
 /******************************************************************************
  * Public Validators
  ******************************************************************************/

openfpga/src/fpga_bitstream/fabric_bitstream.h

@@ -152,11 +152,14 @@ class FabricBitstream {
      * This function is only applicable before any bits are added
      */
     void set_use_address(const bool& enable);
+    void set_address_length(const size_t& length);
+    void set_bl_address_length(const size_t& length);
 
     /* Enable the use of WL-address related data
      * Same priniciple as the set_use_address()  
      */
     void set_use_wl_address(const bool& enable);
+    void set_wl_address_length(const size_t& length);
 
   public:  /* Public Validators */
     char valid_bit_id(const FabricBitId& bit_id) const;
@@ -171,14 +174,17 @@ class FabricBitstream {
     bool use_address_;
     bool use_wl_address_;
 
+    size_t address_length_;
+    size_t wl_address_length_;
+
     /* Address bits: this is designed for memory decoders
      * Here we store the binary format of the address, which can be loaded
      * to the configuration protocol directly 
      *
      * We use a 2-element array, as we may have a BL address and a WL address
      */
-    vtr::vector<FabricBitId, std::vector<char>> bit_addresses_;
-    vtr::vector<FabricBitId, std::vector<char>> bit_wl_addresses_;
+    vtr::vector<FabricBitId, size_t> bit_addresses_;
+    vtr::vector<FabricBitId, size_t> bit_wl_addresses_;
 
     /* Data input (Din) bits: this is designed for memory decoders */
     vtr::vector<FabricBitId, char> bit_dins_;