[FPGA-SPICE] Add pass-gate SPICE netlist writer
This commit is contained in:
tangxifan
parent
9e4353ddf4
commit
51d423e4db
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@ -1,6 +1,6 @@
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/************************************************
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* This file includes functions on
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* outputting Verilog netlists for essential gates
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* outputting SPICE netlists for essential gates
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* which are inverters, buffers, transmission-gates
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* logic gates etc.
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***********************************************/
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@ -22,6 +22,7 @@
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#include "spice_constants.h"
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#include "spice_writer_utils.h"
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#include "spice_passgate.h"
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#include "spice_essential_gates.h"
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/* begin namespace openfpga */
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@ -1046,7 +1047,7 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
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VTR_ASSERT(TECH_LIB_MODEL_TRANSISTOR == tech_lib.model_type(tech_model));
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}
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/* Now branch on netlist writing */
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/* Now branch on netlist writing: for inverter/buffers */
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if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
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if (CIRCUIT_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) {
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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@ -1069,6 +1070,21 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
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/* Finish, go to the next */
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continue;
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}
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/* Now branch on netlist writing: for inverter/buffers */
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if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
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status = print_spice_passgate_subckt(fp,
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module_manager, module_id,
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circuit_lib, circuit_model,
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tech_lib, tech_model);
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if (CMD_EXEC_FATAL_ERROR == status) {
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break;
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}
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/* Finish, go to the next */
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continue;
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}
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}
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/* Close file handler*/
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@ -0,0 +1,338 @@
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/************************************************
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* This file includes functions on
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* outputting SPICE netlists for transmission-gates
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***********************************************/
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#include <fstream>
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#include <cmath>
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#include <iomanip>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "circuit_library_utils.h"
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#include "spice_constants.h"
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#include "spice_writer_utils.h"
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#include "spice_passgate.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Generate the SPICE modeling for the PMOS part of a pass-gate logic
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*
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* This function is created to be shared by pass-transistor and
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* transmission-gate SPICE netlist writer
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*
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* Note:
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* - This function does NOT create a file
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* but requires a file stream created
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* - This function only output SPICE modeling for
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* a pass-gate. Any preprocessing or subckt definition should not be included!
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*******************************************************************/
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static
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int print_spice_passgate_pmos_modeling(std::fstream& fp,
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const std::string& trans_name_postfix,
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const std::string& input_port_name,
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const std::string& gate_port_name,
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const std::string& output_port_name,
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const TechnologyLibrary& tech_lib,
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const TechnologyModelId& tech_model,
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const float& trans_width) {
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if (false == valid_file_stream(fp)) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Write transistor pairs using the technology model */
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fp << "Xpmos_" << trans_name_postfix << " ";
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fp << input_port_name << " ";
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fp << gate_port_name << " ";
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fp << output_port_name << " ";
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fp << "LVDD ";
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fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX;
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fp << " W=" << std::setprecision(10) << trans_width;
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fp << "\n";
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return CMD_EXEC_SUCCESS;
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}
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/********************************************************************
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* Generate the SPICE modeling for the NMOS part of a pass-gate logic
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*
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* This function is created to be shared by pass-transistor and
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* transmission-gate SPICE netlist writer
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*
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* Note:
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* - This function does NOT create a file
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* but requires a file stream created
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* - This function only output SPICE modeling for
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* a pass-gate. Any preprocessing or subckt definition should not be included!
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*******************************************************************/
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static
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int print_spice_passgate_nmos_modeling(std::fstream& fp,
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const std::string& trans_name_postfix,
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const std::string& input_port_name,
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const std::string& gate_port_name,
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const std::string& output_port_name,
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const TechnologyLibrary& tech_lib,
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const TechnologyModelId& tech_model,
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const float& trans_width) {
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if (false == valid_file_stream(fp)) {
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return CMD_EXEC_FATAL_ERROR;
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}
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fp << "Xnmos_" << trans_name_postfix << " ";
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fp << input_port_name << " ";
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fp << gate_port_name << " ";
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fp << output_port_name << " ";
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fp << "LGND ";
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fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX;
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fp << " W=" << std::setprecision(10) << trans_width;
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fp << "\n";
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return CMD_EXEC_SUCCESS;
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}
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/********************************************************************
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* Generate the SPICE subckt for a pass-transistor
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*
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* Schematic
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*
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* sel
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* |
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* ===
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* | |
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* in -- ---out
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*
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*******************************************************************/
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static
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int print_spice_pass_transistor_subckt(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const TechnologyLibrary& tech_lib,
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const TechnologyModelId& tech_model) {
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if (false == valid_file_stream(fp)) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Find the input and output ports:
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* we do NOT support global ports here,
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* it should be handled in another type of inverter subckt (power-gated)
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*/
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std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
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/* Make sure:
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* There is only 2 input port and 1 output port,
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* each size of which is 1
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*/
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VTR_ASSERT(2 == input_ports.size());
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for (const auto& input_port : input_ports) {
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VTR_ASSERT(1 == circuit_lib.port_size(input_port));
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}
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VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
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int status = CMD_EXEC_SUCCESS;
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/* Print the inverter subckt definition */
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print_spice_subckt_definition(fp, module_manager, module_id);
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/* Consider use size/bin to compact layout:
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* Try to size transistors to the max width for each bin
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* The last bin may not reach the max width
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*/
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float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
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float total_nmos_width = circuit_lib.pass_gate_logic_nmos_size(circuit_model)
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* tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
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int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
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float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
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for (int ibin = 0; ibin < num_nmos_bins; ++ibin) {
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float curr_bin_width = regular_nmos_bin_width;
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/* For last bin, we need an irregular width */
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if ((ibin == num_nmos_bins - 1)
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&& (0. != last_nmos_bin_width)) {
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curr_bin_width = last_nmos_bin_width;
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}
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status = print_spice_passgate_nmos_modeling(fp,
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std::to_string(ibin),
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circuit_lib.port_prefix(input_ports[0]),
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circuit_lib.port_prefix(input_ports[1]),
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circuit_lib.port_prefix(output_ports[0]),
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tech_lib,
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tech_model,
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curr_bin_width);
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if (CMD_EXEC_FATAL_ERROR == status) {
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return status;
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}
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}
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print_spice_subckt_end(fp, module_manager.module_name(module_id));
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return status;
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}
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/********************************************************************
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* Generate the SPICE subckt for a transmission gate
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*
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* Schematic
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*
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* selb
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* |
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* o
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* ===
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* | |
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* in -- ---out
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* | |
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* ===
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* |
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* sel
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*
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*******************************************************************/
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static
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int print_spice_transmission_gate_subckt(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const TechnologyLibrary& tech_lib,
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const TechnologyModelId& tech_model) {
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if (false == valid_file_stream(fp)) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Find the input and output ports:
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* we do NOT support global ports here,
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* it should be handled in another type of inverter subckt (power-gated)
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*/
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std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
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/* Make sure:
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* There is only 3 input port and 1 output port,
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* each size of which is 1
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*/
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VTR_ASSERT(3 == input_ports.size());
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for (const auto& input_port : input_ports) {
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VTR_ASSERT(1 == circuit_lib.port_size(input_port));
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}
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VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
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int status = CMD_EXEC_SUCCESS;
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/* Print the inverter subckt definition */
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print_spice_subckt_definition(fp, module_manager, module_id);
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/* Consider use size/bin to compact layout:
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* Try to size transistors to the max width for each bin
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* The last bin may not reach the max width
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*/
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float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
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float total_pmos_width = circuit_lib.pass_gate_logic_pmos_size(circuit_model)
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* tech_lib.model_pn_ratio(tech_model)
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* tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
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int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
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float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
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for (int ibin = 0; ibin < num_pmos_bins; ++ibin) {
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float curr_bin_width = regular_pmos_bin_width;
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/* For last bin, we need an irregular width */
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if ((ibin == num_pmos_bins - 1)
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&& (0. != last_pmos_bin_width)) {
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curr_bin_width = last_pmos_bin_width;
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}
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status = print_spice_passgate_pmos_modeling(fp,
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std::to_string(ibin),
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circuit_lib.port_prefix(input_ports[0]),
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circuit_lib.port_prefix(input_ports[2]),
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circuit_lib.port_prefix(output_ports[0]),
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tech_lib,
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tech_model,
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curr_bin_width);
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if (CMD_EXEC_FATAL_ERROR == status) {
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return status;
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}
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}
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/* Consider use size/bin to compact layout:
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* Try to size transistors to the max width for each bin
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* The last bin may not reach the max width
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*/
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float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
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float total_nmos_width = circuit_lib.pass_gate_logic_nmos_size(circuit_model)
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* tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
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int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
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float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
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for (int ibin = 0; ibin < num_nmos_bins; ++ibin) {
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float curr_bin_width = regular_nmos_bin_width;
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/* For last bin, we need an irregular width */
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if ((ibin == num_nmos_bins - 1)
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&& (0. != last_nmos_bin_width)) {
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curr_bin_width = last_nmos_bin_width;
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}
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status = print_spice_passgate_nmos_modeling(fp,
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std::to_string(ibin),
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circuit_lib.port_prefix(input_ports[0]),
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circuit_lib.port_prefix(input_ports[1]),
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circuit_lib.port_prefix(output_ports[0]),
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tech_lib,
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tech_model,
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curr_bin_width);
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if (CMD_EXEC_FATAL_ERROR == status) {
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return status;
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}
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}
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print_spice_subckt_end(fp, module_manager.module_name(module_id));
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return status;
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}
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/********************************************************************
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* Generate the SPICE subckt for a pass-gate
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*
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* Note:
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* - This function supports both pass-transistor
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* and transmission gates
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*******************************************************************/
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int print_spice_passgate_subckt(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const TechnologyLibrary& tech_lib,
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const TechnologyModelId& tech_model) {
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int status = CMD_EXEC_SUCCESS;
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if (CIRCUIT_MODEL_PASS_GATE_TRANSISTOR == circuit_lib.pass_gate_logic_type(circuit_model)) {
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status = print_spice_pass_transistor_subckt(fp,
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module_manager, module_id,
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circuit_lib, circuit_model,
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tech_lib, tech_model);
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} else if (CIRCUIT_MODEL_PASS_GATE_TRANSMISSION == circuit_lib.is_power_gated(circuit_model)) {
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status = print_spice_transmission_gate_subckt(fp,
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module_manager, module_id,
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circuit_lib, circuit_model,
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tech_lib, tech_model);
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}
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return status;
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}
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} /* end namespace openfpga */
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@ -0,0 +1,30 @@
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#ifndef SPICE_PASSGATE_H
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#define SPICE_PASSGATE_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <string>
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#include <map>
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#include "module_manager.h"
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#include "circuit_library.h"
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#include "technology_library.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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int print_spice_passgate_subckt(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const TechnologyLibrary& tech_lib,
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const TechnologyModelId& tech_model);
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} /* end namespace openfpga */
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#endif
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