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[Tool] Bug fix on the reset stimuli

This commit is contained in:
tangxifan 2021-07-01 19:58:54 -06:00
parent a2cb153d54
commit d0e4f8521f
1 changed files with 1 additions and 1 deletions
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2
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
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@ -230,7 +230,7 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp,
*/
fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl;
fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl;
print_verilog_wire_connection(fp, reset_port, reset_port, true);
print_verilog_register_connection(fp, reset_port, reset_port, true);
fp << "\tend" << std::endl;
}