From d0e4f8521f89e804c6bd9e139a3bff946876728f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Jul 2021 19:58:54 -0600 Subject: [PATCH] [Tool] Bug fix on the reset stimuli --- .../src/fpga_verilog/verilog_formal_random_top_testbench.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 7b54ceb44..7194f208f 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -230,7 +230,7 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp, */ fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl; fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl; - print_verilog_wire_connection(fp, reset_port, reset_port, true); + print_verilog_register_connection(fp, reset_port, reset_port, true); fp << "\tend" << std::endl; }