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adapt bus ports in connection block module builder

This commit is contained in:
tangxifan 2020-06-30 17:50:53 -06:00
parent 2ef083c49d
commit 2e7684b746
8 changed files with 120 additions and 162 deletions
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8
openfpga/src/base/openfpga_naming.cpp
View File

@ -390,7 +390,6 @@ std::string generate_sb_module_track_port_name(const t_rr_type& chan_type,
* Even though, port direction must be provided!
*********************************************************************/
std::string generate_cb_module_track_port_name(const t_rr_type& chan_type,
const size_t& track_id,
const PORTS& port_direction) {
/* Channel must be either CHANX or CHANY */
VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) );
@ -406,19 +405,16 @@ std::string generate_cb_module_track_port_name(const t_rr_type& chan_type,
switch (port_direction) {
case OUT_PORT:
port_name += std::string("out_");
port_name += std::string("out");
break;
case IN_PORT:
port_name += std::string("in_");
port_name += std::string("in");
break;
default:
VTR_LOG_ERROR("Invalid direction of chan_rr_node!\n");
exit(1);
}
/* Add the track id to the port name */
port_name += std::to_string(track_id) + std::string("_");
return port_name;
}

1
openfpga/src/base/openfpga_naming.h
View File

@ -94,7 +94,6 @@ std::string generate_sb_module_track_port_name(const t_rr_type& chan_type,
const PORTS& port_direction);
std::string generate_cb_module_track_port_name(const t_rr_type& chan_type,
const size_t& track_id,
const PORTS& port_direction);
std::string generate_routing_track_middle_output_port_name(const t_rr_type& chan_type,

37
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -133,27 +133,26 @@ std::vector<std::pair<ModulePortId, size_t>> find_switch_block_module_input_port
* Generate an input port for routing multiplexer inside the connection block
* which is the middle output of a routing track
********************************************************************/
ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& chan_rr_node) {
ModulePortId input_port_id;
std::pair<ModulePortId, size_t> find_connection_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& chan_rr_node) {
std::pair<ModulePortId, size_t> input_port_info;
/* Generate the input port object */
switch (rr_graph.node_type(chan_rr_node)) {
case CHANX:
case CHANY: {
/* Create port description for the routing track middle output */
vtr::Point<size_t> port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
int chan_node_track_id = rr_gsb.get_cb_chan_node_index(cb_type, chan_rr_node);
/* Create a port description for the middle output */
std::string input_port_name = generate_cb_module_track_port_name(cb_type,
chan_node_track_id,
IN_PORT);
/* Must find a valid port id in the Switch Block module */
input_port_id = module_manager.find_module_port(cb_module, input_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, input_port_id));
input_port_info.first = module_manager.find_module_port(cb_module, input_port_name);
input_port_info.second = chan_node_track_id;
VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, input_port_info.first));
break;
}
default: /* OPIN, SOURCE, IPIN, SINK are invalid*/
@ -161,7 +160,7 @@ ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_
exit(1);
}
return input_port_id;
return input_port_info;
}
/*********************************************************************
@ -196,13 +195,13 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_
* Generate a list of routing track middle output ports
* for routing multiplexer inside the connection block
********************************************************************/
std::vector<ModulePortId> find_connection_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const std::vector<RRNodeId>& input_rr_nodes) {
std::vector<ModulePortId> input_ports;
std::vector<std::pair<ModulePortId, size_t>> find_connection_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const std::vector<RRNodeId>& input_rr_nodes) {
std::vector<std::pair<ModulePortId, size_t>> input_ports;
for (auto input_rr_node : input_rr_nodes) {
input_ports.push_back(find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node));

24
openfpga/src/fabric/build_routing_module_utils.h
View File

@ -39,12 +39,12 @@ std::vector<std::pair<ModulePortId, size_t>> find_switch_block_module_input_port
const RRGSB& rr_gsb,
const std::vector<RRNodeId>& input_rr_nodes);
ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& chan_rr_node);
std::pair<ModulePortId, size_t> find_connection_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& chan_rr_node);
ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
@ -52,12 +52,12 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_
const RRGSB& rr_gsb,
const RRNodeId& src_rr_node);
std::vector<ModulePortId> find_connection_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const std::vector<RRNodeId>& input_rr_nodes);
std::vector<std::pair<ModulePortId, size_t>> find_connection_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const std::vector<RRNodeId>& input_rr_nodes);
} /* end namespace openfpga */

95
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -471,7 +471,7 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& src_rr_node,
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
const std::map<std::pair<ModulePortId, size_t>, ModuleNetId>& input_port_to_module_nets) {
/* Ensure we have only one 1 driver node */
std::vector<RRNodeId> driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, src_rr_node);
@ -502,23 +502,21 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager,
VTR_ASSERT((CHANX == rr_graph.node_type(driver_rr_node)) || (CHANY == rr_graph.node_type(driver_rr_node)));
/* Create port description for the routing track middle output */
ModulePortId input_port_id = find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_node);
std::pair<ModulePortId, size_t> input_port_info = find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_node);
/* Create port description for input pin of a CLB */
ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_graph, rr_gsb, src_rr_node);
/* The input port and output port must match in size */
BasicPort input_port = module_manager.module_port(cb_module, input_port_id);
BasicPort input_port = module_manager.module_port(cb_module, input_port_info.first);
BasicPort ipin_port = module_manager.module_port(cb_module, ipin_port_id);
VTR_ASSERT(input_port.get_width() == ipin_port.get_width());
VTR_ASSERT(1 == ipin_port.get_width());
/* Create a module net for this short-wire connection */
for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) {
ModuleNetId net = input_port_to_module_nets.at(input_port_id);
/* Skip Configuring the net source, it is done before */
/* Configure the net sink */
module_manager.add_module_net_sink(cb_module, net, cb_module, 0, ipin_port_id, ipin_port.pins()[pin_id]);
}
ModuleNetId net = input_port_to_module_nets.at(input_port_info);
/* Skip Configuring the net source, it is done before */
/* Configure the net sink */
module_manager.add_module_net_sink(cb_module, net, cb_module, 0, ipin_port_id, ipin_port.pins()[0]);
}
/*********************************************************************
@ -535,7 +533,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const e_side& cb_ipin_side,
const size_t& ipin_index,
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
const std::map<std::pair<ModulePortId, size_t>, ModuleNetId>& input_port_to_module_nets) {
const RRNodeId& cur_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index);
/* Check current rr_node is an input pin of a CLB */
VTR_ASSERT(IPIN == rr_graph.node_type(cur_rr_node));
@ -568,7 +566,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
module_manager.set_child_instance_name(cb_module, mux_module, mux_instance_id, mux_instance_name);
/* TODO: Generate input ports that are wired to the input bus of the routing multiplexer */
std::vector<ModulePortId> cb_input_port_ids = find_connection_block_module_input_ports(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_nodes);
std::vector<std::pair<ModulePortId, size_t>> cb_input_port_ids = find_connection_block_module_input_ports(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_nodes);
/* Link input bus port to Switch Block inputs */
std::vector<CircuitPortId> mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
@ -601,9 +599,8 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
/* Check port size should match */
VTR_ASSERT(cb_output_port.get_width() == mux_output_port.get_width());
for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) {
ModuleNetId net = module_manager.create_module_net(cb_module);
/* Configuring the net source */
module_manager.add_module_net_source(cb_module, net, mux_module, mux_instance_id, mux_output_port_id, mux_output_port.pins()[pin_id]);
ModuleNetId net = create_module_source_pin_net(module_manager, cb_module, mux_module, mux_instance_id, mux_output_port_id, mux_output_port.pins()[pin_id]);
/* Configure the net sink */
module_manager.add_module_net_sink(cb_module, net, cb_module, 0, cb_output_port_id, cb_output_port.pins()[pin_id]);
}
@ -649,7 +646,7 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const e_side& cb_ipin_side,
const size_t& ipin_index,
const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
const std::map<std::pair<ModulePortId, size_t>, ModuleNetId>& input_port_to_module_nets) {
const RRNodeId& src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index);
if (1 > rr_graph.node_in_edges(src_rr_node).size()) {
@ -747,22 +744,15 @@ void build_connection_block_module(ModuleManager& module_manager,
/* Add the input and output ports of routing tracks in the channel
* Routing tracks pass through the connection blocks
*/
for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
vtr::Point<size_t> port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
std::string port_name = generate_cb_module_track_port_name(cb_type,
itrack,
IN_PORT);
BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */
module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_INPUT_PORT);
}
for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
vtr::Point<size_t> port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
std::string port_name = generate_cb_module_track_port_name(cb_type,
itrack,
OUT_PORT);
BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */
module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT);
}
std::string chan_input_port_name = generate_cb_module_track_port_name(cb_type,
IN_PORT);
BasicPort chan_input_port(chan_input_port_name, rr_gsb.get_cb_chan_width(cb_type));
ModulePortId chan_input_port_id = module_manager.add_port(cb_module, chan_input_port, ModuleManager::MODULE_INPUT_PORT);
std::string chan_output_port_name = generate_cb_module_track_port_name(cb_type,
OUT_PORT);
BasicPort chan_output_port(chan_output_port_name, rr_gsb.get_cb_chan_width(cb_type));
ModulePortId chan_output_port_id = module_manager.add_port(cb_module, chan_output_port, ModuleManager::MODULE_OUTPUT_PORT);
/* Add the input pins of grids, which are output ports of the connection block */
std::vector<enum e_side> cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type);
@ -780,45 +770,20 @@ void build_connection_block_module(ModuleManager& module_manager,
}
/* Create a cache (fast look up) for module nets whose source are input ports */
std::map<ModulePortId, ModuleNetId> input_port_to_module_nets;
std::map<std::pair<ModulePortId, size_t>, ModuleNetId> input_port_to_module_nets;
/* Generate short-wire connection for each routing track :
* Each input port is short-wired to its output port and middle output port
* Each input port is short-wired to its output port
*
* in[i] ----------> out[i]
* |
* +-----> mid_out[i]
*/
for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
vtr::Point<size_t> port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
/* Create a port description for the input */
std::string input_port_name = generate_cb_module_track_port_name(cb_type,
itrack,
IN_PORT);
ModulePortId input_port_id = module_manager.find_module_port(cb_module, input_port_name);
BasicPort input_port = module_manager.module_port(cb_module, input_port_id);
/* Create a port description for the output */
std::string output_port_name = generate_cb_module_track_port_name(cb_type,
itrack,
OUT_PORT);
ModulePortId output_port_id = module_manager.find_module_port(cb_module, output_port_name);
BasicPort output_port = module_manager.module_port(cb_module, output_port_id);
/* Ensure port size matching */
VTR_ASSERT(1 == input_port.get_width());
VTR_ASSERT(input_port.get_width() == output_port.get_width());
/* Create short-wires: input port ---> output port
* Do short-wires: input port ---> middle output port
*/
for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) {
ModuleNetId net = module_manager.create_module_net(cb_module);
module_manager.add_module_net_source(cb_module, net, cb_module, 0, input_port_id, input_port.pins()[pin_id]);
module_manager.add_module_net_sink(cb_module, net, cb_module, 0, output_port_id, output_port.pins()[pin_id]);
/* Cache the module net */
input_port_to_module_nets[input_port_id] = net;
}
/* Create short-wires: input port ---> output port */
VTR_ASSERT(chan_input_port.get_width() == chan_output_port.get_width());
for (size_t pin_id = 0; pin_id < chan_input_port.pins().size(); ++pin_id) {
ModuleNetId net = create_module_source_pin_net(module_manager, cb_module, cb_module, 0, chan_input_port_id, chan_input_port.pins()[pin_id]);
module_manager.add_module_net_sink(cb_module, net, cb_module, 0, chan_output_port_id, chan_output_port.pins()[pin_id]);
/* Cache the module net */
input_port_to_module_nets[std::pair<ModulePortId, size_t>(chan_input_port_id, chan_input_port.pins()[pin_id])] = net;
}
/* Add sub modules of routing multiplexers or direct interconnect*/

29
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -571,29 +571,22 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager,
VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack));
}
std::string cb_port_name = generate_cb_module_track_port_name(cb_type,
itrack,
cb_port_direction);
ModulePortId cb_port_id = module_manager.find_module_port(cb_module_id, cb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module_id, cb_port_id));
BasicPort cb_port = module_manager.module_port(cb_module_id, cb_port_id);
/* Source and sink port should match in size */
VTR_ASSERT(1 == cb_port.get_width());
/* Create a net for each pin */
for (size_t pin_id = 0; pin_id < cb_port.pins().size(); ++pin_id) {
/* Configure the net source and sink:
* If sb port is an output (source), cb port is an input (sink)
* If sb port is an input (sink), cb port is an output (source)
*/
if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) {
ModuleNetId net = create_module_source_pin_net(module_manager, top_module, sb_module_id, sb_instance, sb_port_id, itrack / 2);
module_manager.add_module_net_sink(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]);
} else {
VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack));
ModuleNetId net = create_module_source_pin_net(module_manager, top_module, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]);
module_manager.add_module_net_sink(top_module, net, sb_module_id, sb_instance, sb_port_id, itrack / 2);
}
/* Configure the net source and sink:
* If sb port is an output (source), cb port is an input (sink)
* If sb port is an input (sink), cb port is an output (source)
*/
if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) {
ModuleNetId net = create_module_source_pin_net(module_manager, top_module, sb_module_id, sb_instance, sb_port_id, itrack / 2);
module_manager.add_module_net_sink(top_module, net, cb_module_id, cb_instance, cb_port_id, itrack);
} else {
VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack));
ModuleNetId net = create_module_source_pin_net(module_manager, top_module, cb_module_id, cb_instance, cb_port_id, itrack);
module_manager.add_module_net_sink(top_module, net, sb_module_id, sb_instance, sb_port_id, itrack / 2);
}
}
}

23
openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp
View File

@ -76,16 +76,17 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
/* Disable both input of the routing track if it is not used! */
std::string port_name = generate_cb_module_track_port_name(cb_type,
itrack,
IN_PORT);
/* Ensure we have this port in the module! */
ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
BasicPort chan_port(module_manager.module_port(cb_module, module_port).get_name(),
itrack, itrack);
fp << "set_disable_timing ";
fp << cb_instance_name << "/";
fp << generate_sdc_port(module_manager.module_port(cb_module, module_port));
fp << generate_sdc_port(chan_port);
fp << std::endl;
}
@ -99,16 +100,17 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
/* Disable both input of the routing track if it is not used! */
std::string port_name = generate_cb_module_track_port_name(cb_type,
itrack,
OUT_PORT);
/* Ensure we have this port in the module! */
ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
BasicPort chan_port(module_manager.module_port(cb_module, module_port).get_name(),
itrack, itrack);
fp << "set_disable_timing ";
fp << cb_instance_name << "/";
fp << generate_sdc_port(module_manager.module_port(cb_module, module_port));
fp << generate_sdc_port(chan_port);
fp << std::endl;
}
@ -181,7 +183,6 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
/* Disable both input of the routing track if it is not used! */
std::string port_name = generate_cb_module_track_port_name(cb_type,
itrack,
OUT_PORT);
/* Ensure we have this port in the module! */
@ -190,12 +191,12 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
AtomNetId mapped_atom_net = atom_ctx.lookup.atom_net(routing_annotation.rr_node_net(chan_node));
disable_analysis_module_input_port_net_sinks(fp,
module_manager, cb_module,
cb_instance_name,
module_port,
mapped_atom_net,
mux_instance_to_net_map);
disable_analysis_module_input_pin_net_sinks(fp, module_manager, cb_module,
cb_instance_name,
module_port, itrack,
mapped_atom_net,
mux_instance_to_net_map);
}
}

65
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
View File

@ -343,15 +343,15 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
output_rr_node);
/* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */
std::vector<ModulePortId> module_input_ports = find_connection_block_module_input_ports(module_manager,
cb_module,
rr_graph,
rr_gsb,
cb_type,
input_rr_nodes);
std::vector<std::pair<ModulePortId, size_t>> module_input_ports = find_connection_block_module_input_ports(module_manager,
cb_module,
rr_graph,
rr_gsb,
cb_type,
input_rr_nodes);
/* Find timing constraints for each path (edge) */
std::map<ModulePortId, float> switch_delays;
std::map<std::pair<ModulePortId, size_t>, float> switch_delays;
size_t edge_counter = 0;
for (const RREdgeId& edge : rr_graph.node_configurable_in_edges(output_rr_node)) {
/* Get the switch delay */
@ -361,27 +361,34 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
}
/* Find the starting points */
for (const ModulePortId& module_input_port : module_input_ports) {
for (const std::pair<ModulePortId, size_t>& module_input_port : module_input_ports) {
/* If we have a zero-delay path to contrain, we will skip unless users want so */
if ( (false == constrain_zero_delay_paths)
&& (0. == switch_delays[module_input_port]) ) {
continue;
}
BasicPort input_port(module_manager.module_port(cb_module, module_input_port.first).get_name(),
module_input_port.second,
module_input_port.second);
BasicPort output_port = module_manager.module_port(cb_module, module_output_port);
/* Constrain a path */
if (true == hierarchical) {
print_pnr_sdc_constrain_port2port_timing(fp,
module_manager,
cb_module, module_input_port,
cb_module, module_output_port,
switch_delays[module_input_port] / time_unit);
print_pnr_sdc_constrain_max_delay(fp,
std::string(),
generate_sdc_port(input_port),
std::string(),
generate_sdc_port(output_port),
switch_delays[module_input_port] / time_unit);
} else {
VTR_ASSERT_SAFE(false == hierarchical);
print_pnr_sdc_constrain_max_delay(fp,
std::string(module_path),
generate_sdc_port(module_manager.module_port(cb_module, module_input_port)),
generate_sdc_port(input_port),
std::string(module_path),
generate_sdc_port(module_manager.module_port(cb_module, module_output_port)),
generate_sdc_port(output_port),
switch_delays[module_input_port] / time_unit);
}
@ -429,21 +436,17 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
/* Create a port description for the input */
std::string input_port_name = generate_cb_module_track_port_name(cb_type,
itrack,
IN_PORT);
ModulePortId input_port_id = module_manager.find_module_port(cb_module, input_port_name);
BasicPort input_port = module_manager.module_port(cb_module, input_port_id);
BasicPort input_port(module_manager.module_port(cb_module, input_port_id).get_name(),
itrack, itrack);
/* Create a port description for the output */
std::string output_port_name = generate_cb_module_track_port_name(cb_type,
itrack,
OUT_PORT);
ModulePortId output_port_id = module_manager.find_module_port(cb_module, output_port_name);
BasicPort output_port = module_manager.module_port(cb_module, output_port_id);
/* Ensure port size matching */
VTR_ASSERT(1 == input_port.get_width());
VTR_ASSERT(input_port.get_width() == output_port.get_width());
BasicPort output_port(module_manager.module_port(cb_module, output_port_id).get_name(),
itrack, itrack);
/* Connection block routing segment ids for each track */
RRSegmentId segment_id = rr_gsb.get_chan_node_segment(rr_gsb.get_cb_chan_side(cb_type), itrack);
@ -464,18 +467,20 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
/* Constrain a path with routing segment delay */
if (true == hierarchical) {
print_pnr_sdc_constrain_port2port_timing(fp,
module_manager,
cb_module, input_port_id,
cb_module, output_port_id,
routing_segment_delay / time_unit);
print_pnr_sdc_constrain_max_delay(fp,
std::string(),
generate_sdc_port(input_port),
std::string(),
generate_sdc_port(output_port),
routing_segment_delay / time_unit);
} else {
VTR_ASSERT_SAFE(false == hierarchical);
print_pnr_sdc_constrain_max_delay(fp,
std::string(module_path),
generate_sdc_port(module_manager.module_port(cb_module, input_port_id)),
generate_sdc_port(input_port),
std::string(module_path),
generate_sdc_port(module_manager.module_port(cb_module, output_port_id)),
generate_sdc_port(output_port),
routing_segment_delay / time_unit);
}
}