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[Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base

This commit is contained in:
tangxifan 2021-06-24 17:13:36 -06:00
parent 5364d8104f
commit 549657e1fb
2 changed files with 0 additions and 7 deletions
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6
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
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@ -212,12 +212,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
fp << std::endl;
}
/* To enable manualy checked simulation */
if (true == verilog_testbench_opts.print_top_testbench()) {
print_verilog_define_flag(fp, std::string(INITIAL_SIMULATION_FLAG), 1);
fp << std::endl;
}
/* To enable auto-checked simulation */
if ( (true == verilog_testbench_opts.print_preconfig_top_testbench())
|| (true == verilog_testbench_opts.print_top_testbench()) ) {

1
openfpga/src/fpga_verilog/verilog_constants.h
View File

@ -8,7 +8,6 @@ constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (
constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation
constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification
constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification