[Tool] Add signal_init option to preconfigured fabric wrapper writer
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@ -128,6 +128,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
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CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
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CommandOptionId opt_default_net_type = cmd.option("default_net_type");
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CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
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CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
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@ -139,6 +140,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
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options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
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options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
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options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
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options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
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options.set_print_formal_verification_top_netlist(true);
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if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
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options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
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@ -149,6 +149,9 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga:
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/* Add an option '--support_icarus_simulator' */
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shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
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/* add an option '--include_signal_init' */
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shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
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/* add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "enable verbose output");
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