[FPGA-SPICE] Add SPICE writer for fpga top module
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@ -18,6 +18,7 @@
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#include "spice_submodule.h"
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#include "spice_routing.h"
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#include "spice_grid.h"
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#include "spice_top_module.h"
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/* Header file for this source file */
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#include "spice_api.h"
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@ -107,6 +108,18 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
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lb_dir_path,
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options.verbose_output());
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/* Generate FPGA fabric */
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print_spice_top_module(netlist_manager,
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module_manager,
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src_dir_path);
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/* Generate an netlist including all the fabric-related netlists */
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/*
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print_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
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src_dir_path,
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circuit_lib);
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*/
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/* Given a brief stats on how many Spice modules have been written to files */
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VTR_LOGV(options.verbose_output(),
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"Written %lu SPICE modules in total\n",
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@ -0,0 +1,76 @@
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/********************************************************************
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* This file includes functions that are used to print the top-level
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* module for the FPGA fabric in SPICE format
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*******************************************************************/
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#include <fstream>
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#include <map>
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "openfpga_naming.h"
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#include "spice_constants.h"
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#include "spice_writer_utils.h"
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#include "spice_subckt_writer.h"
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#include "spice_top_module.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Print the top-level module for the FPGA fabric in SPICE format
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* This function will
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* 1. name the top-level module
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* 2. include dependent netlists
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* - User defined netlists
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* - Auto-generated netlists
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* 3. Add the submodules to the top-level graph
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* 4. Add module nets to connect datapath ports
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* 5. Add module nets/submodules to connect configuration ports
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*******************************************************************/
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void print_spice_top_module(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const std::string& spice_dir) {
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/* Create a module as the top-level fabric, and add it to the module manager */
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.find_module(top_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(top_module));
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/* Create the file name for SPICE netlist */
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std::string spice_fname(spice_dir + generate_fpga_top_netlist_name(std::string(SPICE_NETLIST_FILE_POSTFIX)));
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VTR_LOG("Writing SPICE netlist for top-level module of FPGA fabric '%s'...",
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spice_fname.c_str());
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/* Create the file stream */
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std::fstream fp;
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fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(spice_fname.c_str(), fp);
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print_spice_file_header(fp, std::string("Top-level SPICE subckt for FPGA"));
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/* Write the module content in Verilog format */
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write_spice_subckt_to_file(fp, module_manager, top_module);
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/* Add an empty line as a splitter */
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fp << std::endl;
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/* Close file handler */
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fp.close();
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/* Add fname to the netlist name list */
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NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
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VTR_ASSERT(NetlistId::INVALID() != nlist_id);
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netlist_manager.set_netlist_type(nlist_id, NetlistManager::TOP_MODULE_NETLIST);
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VTR_LOG("Done\n");
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}
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} /* end namespace openfpga */
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@ -0,0 +1,24 @@
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#ifndef SPICE_TOP_MODULE_H
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#define SPICE_TOP_MODULE_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <string>
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#include "module_manager.h"
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#include "netlist_manager.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void print_spice_top_module(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const std::string& spice_dir);
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} /* end namespace openfpga */
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#endif
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