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[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes

This commit is contained in:
tangxifan 2021-04-17 17:45:50 -06:00
parent d95a1e2776
commit 02ca51d84b
1 changed files with 106 additions and 11 deletions
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117
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -258,22 +258,17 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp,
}
/********************************************************************
* Wire the global ports of FPGA fabric to local wires
* Wire the global clock ports of FPGA fabric to local wires
*******************************************************************/
static
void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const PinConstraints& pin_constraints,
const FabricGlobalPortInfo& fabric_global_port_info,
const SimulationSetting& simulation_parameters,
const bool& active_global_prog_reset,
const bool& active_global_prog_set) {
void print_verilog_top_testbench_global_clock_ports_stimuli(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const FabricGlobalPortInfo& fabric_global_port_info,
const SimulationSetting& simulation_parameters) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_comment(fp, std::string("----- Begin connecting global ports of FPGA fabric to stimuli -----"));
/* Connect global clock ports to operating or programming clock signal */
for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) {
if (false == fabric_global_port_info.global_port_is_clock(fabric_global_port)) {
@ -318,6 +313,18 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
1 == fabric_global_port_info.global_port_default_value(fabric_global_port));
}
}
}
/********************************************************************
* Wire the global config done ports of FPGA fabric to local wires
*******************************************************************/
static
void print_verilog_top_testbench_global_config_done_ports_stimuli(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const FabricGlobalPortInfo& fabric_global_port_info) {
/* Validate the file stream */
valid_file_stream(fp);
/* Connect global configuration done ports to configuration done signal */
for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) {
@ -342,6 +349,20 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
stimuli_config_done_port,
1 == fabric_global_port_info.global_port_default_value(fabric_global_port));
}
}
/********************************************************************
* Wire the global reset ports of FPGA fabric to local wires
*******************************************************************/
static
void print_verilog_top_testbench_global_reset_ports_stimuli(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const PinConstraints& pin_constraints,
const FabricGlobalPortInfo& fabric_global_port_info,
const bool& active_global_prog_reset) {
/* Validate the file stream */
valid_file_stream(fp);
/* Connect global reset ports to operating or programming reset signal */
for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) {
@ -412,6 +433,19 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
}
}
}
}
/********************************************************************
* Wire the global set ports of FPGA fabric to local wires
*******************************************************************/
static
void print_verilog_top_testbench_global_set_ports_stimuli(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const FabricGlobalPortInfo& fabric_global_port_info,
const bool& active_global_prog_set) {
/* Validate the file stream */
valid_file_stream(fp);
/* Connect global set ports to operating or programming set signal */
for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) {
@ -463,6 +497,18 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
std::vector<size_t>(1, fabric_global_port_info.global_port_default_value(fabric_global_port)));
}
}
}
/********************************************************************
* Wire the regular global ports of FPGA fabric to local wires
*******************************************************************/
static
void print_verilog_top_testbench_regular_global_ports_stimuli(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const FabricGlobalPortInfo& fabric_global_port_info) {
/* Validate the file stream */
valid_file_stream(fp);
/* For the rest of global ports, wire them to constant signals */
for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) {
@ -503,6 +549,55 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
std::vector<size_t> default_values(module_port.get_width(), fabric_global_port_info.global_port_default_value(fabric_global_port));
print_verilog_wire_constant_values(fp, module_port, default_values);
}
}
/********************************************************************
* Wire the global ports of FPGA fabric to local wires
*******************************************************************/
static
void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const PinConstraints& pin_constraints,
const FabricGlobalPortInfo& fabric_global_port_info,
const SimulationSetting& simulation_parameters,
const bool& active_global_prog_reset,
const bool& active_global_prog_set) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_comment(fp, std::string("----- Begin connecting global ports of FPGA fabric to stimuli -----"));
print_verilog_top_testbench_global_clock_ports_stimuli(fp,
module_manager,
top_module,
fabric_global_port_info,
simulation_parameters);
print_verilog_top_testbench_global_config_done_ports_stimuli(fp,
module_manager,
top_module,
fabric_global_port_info);
print_verilog_top_testbench_global_reset_ports_stimuli(fp,
module_manager,
top_module,
pin_constraints,
fabric_global_port_info,
active_global_prog_reset);
print_verilog_top_testbench_global_set_ports_stimuli(fp,
module_manager,
top_module,
fabric_global_port_info,
active_global_prog_set);
print_verilog_top_testbench_regular_global_ports_stimuli(fp,
module_manager,
top_module,
fabric_global_port_info);
print_verilog_comment(fp, std::string("----- End connecting global ports of FPGA fabric to stimuli -----"));
}