[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
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tangxifan
parent
6f09f5f7ad
commit
1aac3197eb
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@ -29,46 +29,14 @@
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#include "verilog_constants.h"
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#include "verilog_writer_utils.h"
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#include "verilog_testbench_utils.h"
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#include "verilog_top_testbench_memory_bank.h"
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#include "verilog_top_testbench.h"
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#include "verilog_top_testbench_constants.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Local variables used only in this file
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*******************************************************************/
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constexpr char* TOP_TESTBENCH_REFERENCE_INSTANCE_NAME = "REF_DUT";
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constexpr char* TOP_TESTBENCH_FPGA_INSTANCE_NAME = "FPGA_DUT";
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constexpr char* TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX = "_benchmark";
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constexpr char* TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX = "_fpga";
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constexpr char* TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX = "_flag";
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constexpr char* TOP_TESTBENCH_PROG_TASK_NAME = "prog_cycle_task";
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constexpr char* TOP_TESTBENCH_SIM_START_PORT_NAME = "sim_start";
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constexpr char* TOP_TESTBENCH_ERROR_COUNTER = "nb_error";
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constexpr char* TOP_TB_RESET_PORT_NAME = "greset";
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constexpr char* TOP_TB_SET_PORT_NAME = "gset";
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constexpr char* TOP_TB_PROG_RESET_PORT_NAME = "prog_reset";
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constexpr char* TOP_TB_PROG_SET_PORT_NAME = "prog_set";
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constexpr char* TOP_TB_CONFIG_DONE_PORT_NAME = "config_done";
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constexpr char* TOP_TB_OP_CLOCK_PORT_NAME = "op_clock";
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constexpr char* TOP_TB_OP_CLOCK_PORT_PREFIX = "operating_clk_";
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constexpr char* TOP_TB_PROG_CLOCK_PORT_NAME = "prog_clock";
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constexpr char* TOP_TB_INOUT_REG_POSTFIX = "_reg";
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constexpr char* TOP_TB_CLOCK_REG_POSTFIX = "_reg";
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constexpr char* TOP_TB_BITSTREAM_LENGTH_VARIABLE = "BITSTREAM_LENGTH";
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constexpr char* TOP_TB_BITSTREAM_WIDTH_VARIABLE = "BITSTREAM_WIDTH";
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constexpr char* TOP_TB_BITSTREAM_MEM_REG_NAME = "bit_mem";
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constexpr char* TOP_TB_BITSTREAM_INDEX_REG_NAME = "bit_index";
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constexpr char* TOP_TB_BITSTREAM_ITERATOR_REG_NAME = "ibit";
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constexpr char* TOP_TB_BITSTREAM_SKIP_FLAG_REG_NAME = "skip_bits";
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constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX = "_autocheck_top_tb";
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/********************************************************************
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* Generate a simulation clock port name
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* This function is designed to produce a uniform clock naming for these ports
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@ -1735,6 +1703,13 @@ void print_verilog_full_testbench_bitstream(std::fstream& fp,
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module_manager, top_module,
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fabric_bitstream);
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break;
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case CONFIG_MEM_QL_MEMORY_BANK:
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print_verilog_full_testbench_ql_memory_bank_bitstream(fp, bitstream_file,
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fast_configuration,
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bit_value_to_skip,
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module_manager, top_module,
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fabric_bitstream);
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break;
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case CONFIG_MEM_FRAME_BASED:
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print_verilog_full_testbench_frame_decoder_bitstream(fp, bitstream_file,
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fast_configuration,
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@ -0,0 +1,42 @@
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#ifndef VERILOG_TOP_TESTBENCH_CONSTANTS
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#define VERILOG_TOP_TESTBENCH_CONSTANTS
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/* begin namespace openfpga */
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namespace openfpga {
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constexpr char* TOP_TESTBENCH_REFERENCE_INSTANCE_NAME = "REF_DUT";
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constexpr char* TOP_TESTBENCH_FPGA_INSTANCE_NAME = "FPGA_DUT";
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constexpr char* TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX = "_benchmark";
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constexpr char* TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX = "_fpga";
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constexpr char* TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX = "_flag";
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constexpr char* TOP_TESTBENCH_PROG_TASK_NAME = "prog_cycle_task";
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constexpr char* TOP_TESTBENCH_SIM_START_PORT_NAME = "sim_start";
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constexpr char* TOP_TESTBENCH_ERROR_COUNTER = "nb_error";
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constexpr char* TOP_TB_RESET_PORT_NAME = "greset";
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constexpr char* TOP_TB_SET_PORT_NAME = "gset";
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constexpr char* TOP_TB_PROG_RESET_PORT_NAME = "prog_reset";
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constexpr char* TOP_TB_PROG_SET_PORT_NAME = "prog_set";
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constexpr char* TOP_TB_CONFIG_DONE_PORT_NAME = "config_done";
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constexpr char* TOP_TB_OP_CLOCK_PORT_NAME = "op_clock";
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constexpr char* TOP_TB_OP_CLOCK_PORT_PREFIX = "operating_clk_";
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constexpr char* TOP_TB_PROG_CLOCK_PORT_NAME = "prog_clock";
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constexpr char* TOP_TB_INOUT_REG_POSTFIX = "_reg";
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constexpr char* TOP_TB_CLOCK_REG_POSTFIX = "_reg";
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constexpr char* TOP_TB_BITSTREAM_LENGTH_VARIABLE = "BITSTREAM_LENGTH";
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constexpr char* TOP_TB_BITSTREAM_WIDTH_VARIABLE = "BITSTREAM_WIDTH";
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constexpr char* TOP_TB_BITSTREAM_MEM_REG_NAME = "bit_mem";
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constexpr char* TOP_TB_BITSTREAM_INDEX_REG_NAME = "bit_index";
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constexpr char* TOP_TB_BITSTREAM_ITERATOR_REG_NAME = "ibit";
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constexpr char* TOP_TB_BITSTREAM_SKIP_FLAG_REG_NAME = "skip_bits";
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constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX = "_autocheck_top_tb";
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} /* end namespace openfpga */
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#endif
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@ -0,0 +1,175 @@
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/********************************************************************
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* This file includes functions that are used to create
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* an auto-check top-level testbench for a FPGA fabric
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*******************************************************************/
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#include <fstream>
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#include <iomanip>
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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#include "vtr_assert.h"
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#include "vtr_time.h"
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/* Headers from openfpgautil library */
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#include "openfpga_port.h"
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#include "openfpga_digest.h"
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#include "bitstream_manager_utils.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "simulation_utils.h"
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#include "openfpga_atom_netlist_utils.h"
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#include "fast_configuration.h"
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#include "fabric_bitstream_utils.h"
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#include "fabric_global_port_info_utils.h"
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#include "verilog_constants.h"
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#include "verilog_writer_utils.h"
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#include "verilog_testbench_utils.h"
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#include "verilog_top_testbench_memory_bank.h"
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#include "verilog_top_testbench_constants.h"
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/* begin namespace openfpga */
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namespace openfpga {
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void print_verilog_full_testbench_ql_memory_bank_bitstream(std::fstream& fp,
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const std::string& bitstream_file,
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const bool& fast_configuration,
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const bool& bit_value_to_skip,
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const ModuleManager& module_manager,
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const ModuleId& top_module,
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const FabricBitstream& fabric_bitstream) {
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/* Validate the file stream */
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valid_file_stream(fp);
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/* Reorganize the fabric bitstream by the same address across regions */
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MemoryBankFabricBitstream fabric_bits_by_addr = build_memory_bank_fabric_bitstream_by_address(fabric_bitstream);
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/* For fast configuration, identify the final bitstream size to be used */
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size_t num_bits_to_skip = 0;
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if (true == fast_configuration) {
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num_bits_to_skip = fabric_bits_by_addr.size() - find_memory_bank_fast_configuration_fabric_bitstream_size(fabric_bitstream, bit_value_to_skip);
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}
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VTR_ASSERT(num_bits_to_skip < fabric_bits_by_addr.size());
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/* Feed address and data input pair one by one
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* Note: the first cycle is reserved for programming reset
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* We should give dummy values
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*/
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ModulePortId bl_addr_port_id = module_manager.find_module_port(top_module,
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std::string(DECODER_BL_ADDRESS_PORT_NAME));
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BasicPort bl_addr_port = module_manager.module_port(top_module, bl_addr_port_id);
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std::vector<size_t> initial_bl_addr_values(bl_addr_port.get_width(), 0);
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ModulePortId wl_addr_port_id = module_manager.find_module_port(top_module,
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std::string(DECODER_WL_ADDRESS_PORT_NAME));
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BasicPort wl_addr_port = module_manager.module_port(top_module, wl_addr_port_id);
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std::vector<size_t> initial_wl_addr_values(wl_addr_port.get_width(), 0);
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ModulePortId din_port_id = module_manager.find_module_port(top_module,
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std::string(DECODER_DATA_IN_PORT_NAME));
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BasicPort din_port = module_manager.module_port(top_module, din_port_id);
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std::vector<size_t> initial_din_values(din_port.get_width(), 0);
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/* Define a constant for the bitstream length */
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print_verilog_define_flag(fp, std::string(TOP_TB_BITSTREAM_LENGTH_VARIABLE), fabric_bits_by_addr.size() - num_bits_to_skip);
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print_verilog_define_flag(fp, std::string(TOP_TB_BITSTREAM_WIDTH_VARIABLE), bl_addr_port.get_width() + wl_addr_port.get_width() + din_port.get_width());
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/* Declare local variables for bitstream loading in Verilog */
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print_verilog_comment(fp, "----- Virtual memory to store the bitstream from external file -----");
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fp << "reg [0:`" << TOP_TB_BITSTREAM_WIDTH_VARIABLE << " - 1] ";
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fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[0:`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << " - 1];";
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fp << std::endl;
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fp << "reg [$clog2(`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << "):0] " << TOP_TB_BITSTREAM_INDEX_REG_NAME << ";" << std::endl;
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print_verilog_comment(fp, "----- Preload bitstream file to a virtual memory -----");
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fp << "initial begin" << std::endl;
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fp << "\t";
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fp << "$readmemb(\"" << bitstream_file << "\", " << TOP_TB_BITSTREAM_MEM_REG_NAME << ");";
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fp << std::endl;
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print_verilog_comment(fp, "----- Bit-Line Address port default input -----");
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fp << "\t";
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fp << generate_verilog_port_constant_values(bl_addr_port, initial_bl_addr_values);
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fp << ";";
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fp << std::endl;
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print_verilog_comment(fp, "----- Word-Line Address port default input -----");
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fp << "\t";
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fp << generate_verilog_port_constant_values(wl_addr_port, initial_wl_addr_values);
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fp << ";";
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fp << std::endl;
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print_verilog_comment(fp, "----- Data-input port default input -----");
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fp << "\t";
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fp << generate_verilog_port_constant_values(din_port, initial_din_values);
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fp << ";";
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fp << std::endl;
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fp << "\t";
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fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " <= 0";
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fp << ";";
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fp << std::endl;
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fp << "end";
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fp << std::endl;
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print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----");
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BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME) + std::string(TOP_TB_CLOCK_REG_POSTFIX), 1);
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fp << "always";
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fp << " @(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ")";
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fp << " begin";
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fp << std::endl;
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fp << "\t";
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fp << "if (";
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fp << TOP_TB_BITSTREAM_INDEX_REG_NAME;
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fp << " >= ";
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fp << "`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE;
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fp << ") begin";
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fp << std::endl;
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BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
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fp << "\t\t";
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std::vector<size_t> config_done_final_values(config_done_port.get_width(), 1);
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fp << generate_verilog_port_constant_values(config_done_port, config_done_final_values, true);
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fp << ";" << std::endl;
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fp << "\t";
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fp << "end else begin";
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fp << std::endl;
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fp << "\t\t";
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fp << "{";
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fp << generate_verilog_port(VERILOG_PORT_CONKT, bl_addr_port);
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fp << ", ";
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fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_addr_port);
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fp << ", ";
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fp << generate_verilog_port(VERILOG_PORT_CONKT, din_port);
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fp << "}";
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fp << " <= ";
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fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[" << TOP_TB_BITSTREAM_INDEX_REG_NAME << "]";
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fp << ";" << std::endl;
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fp << "\t\t";
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fp << TOP_TB_BITSTREAM_INDEX_REG_NAME;
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fp << " <= ";
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fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " + 1";
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fp << ";" << std::endl;
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fp << "\t";
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fp << "end";
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fp << std::endl;
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fp << "end";
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fp << std::endl;
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print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
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}
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} /* end namespace openfpga */
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@ -0,0 +1,43 @@
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#ifndef VERILOG_TOP_TESTBENCH_MEMORY_BANK
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#define VERILOG_TOP_TESTBENCH_MEMORY_BANK
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <string>
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#include <vector>
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#include "module_manager.h"
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#include "bitstream_manager.h"
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#include "fabric_bitstream.h"
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#include "circuit_library.h"
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#include "config_protocol.h"
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#include "vpr_context.h"
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#include "pin_constraints.h"
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#include "io_location_map.h"
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#include "fabric_global_port_info.h"
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#include "vpr_netlist_annotation.h"
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#include "simulation_setting.h"
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#include "verilog_testbench_options.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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/**
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* @brief Print stimulus for a FPGA fabric with a memory bank configuration protocol
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* where configuration bits are programming in serial (one by one)
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*/
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void print_verilog_full_testbench_ql_memory_bank_bitstream(std::fstream& fp,
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const std::string& bitstream_file,
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const bool& fast_configuration,
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const bool& bit_value_to_skip,
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const ModuleManager& module_manager,
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const ModuleId& top_module,
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const FabricBitstream& fabric_bitstream);
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} /* end namespace openfpga */
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#endif
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