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reserve block bits to save memory

This commit is contained in:
tangxifan 2020-07-02 21:52:32 -06:00
parent 043fb54206
commit 246b4d5ac6
4 changed files with 17 additions and 0 deletions
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8
libopenfpga/libfpgabitstream/src/bitstream_manager.cpp
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@ -220,6 +220,14 @@ void BitstreamManager::add_child_block(const ConfigBlockId& parent_block, const
parent_block_ids_[child_block] = parent_block;
}
void BitstreamManager::reserve_block_bits(const ConfigBlockId& block,
const size_t& num_bits) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block));
block_bit_ids_[block].reserve(num_bits);
}
void BitstreamManager::add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block));

4
libopenfpga/libfpgabitstream/src/bitstream_manager.h
View File

@ -170,6 +170,10 @@ class BitstreamManager {
/* Set a block as a child block of another */
void add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block);
/* Reserve a number of configuration bits for a block */
void reserve_block_bits(const ConfigBlockId& block,
const size_t& num_bits);
/* Add a configuration bit to a block */
void add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit);

3
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -106,6 +106,7 @@ void build_primitive_bitstream(BitstreamManager& bitstream_manager,
bitstream_manager.add_child_block(parent_configurable_block, mem_block);
/* Add the bitstream to the bitstream manager */
bitstream_manager.reserve_block_bits(mem_block, mode_select_bitstream.size());
for (const bool& bit : mode_select_bitstream) {
ConfigBitId config_bit = bitstream_manager.add_bit(bit);
/* Link the memory bits to the mux mem block */
@ -214,6 +215,7 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag
VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
/* Add the bistream to the bitstream manager */
bitstream_manager.reserve_block_bits(mux_mem_block, mux_bitstream.size());
for (const bool& bit : mux_bitstream) {
ConfigBitId config_bit = bitstream_manager.add_bit(bit);
/* Link the memory bits to the mux mem block */
@ -467,6 +469,7 @@ void build_lut_bitstream(BitstreamManager& bitstream_manager,
bitstream_manager.add_child_block(parent_configurable_block, mem_block);
/* Add the bitstream to the bitstream manager */
bitstream_manager.reserve_block_bits(mem_block, lut_bitstream.size());
for (const bool& bit : lut_bitstream) {
ConfigBitId config_bit = bitstream_manager.add_bit(bit);
/* Link the memory bits to the mux mem block */

2
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -98,6 +98,7 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
/* Add the bistream to the bitstream manager */
bitstream_manager.reserve_block_bits(mux_mem_block, mux_bitstream.size());
for (const bool& bit : mux_bitstream) {
ConfigBitId config_bit = bitstream_manager.add_bit(bit);
/* Link the memory bits to the mux mem block */
@ -291,6 +292,7 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
/* Add the bistream to the bitstream manager */
bitstream_manager.reserve_block_bits(mux_mem_block, mux_bitstream.size());
for (const bool& bit : mux_bitstream) {
ConfigBitId config_bit = bitstream_manager.add_bit(bit);
/* Link the memory bits to the mux mem block */