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bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream

This commit is contained in:
tangxifan 2020-07-03 15:56:20 -06:00
parent 2a9377b3f4
commit 8067a13346
1 changed files with 2 additions and 2 deletions
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4
openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
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@ -425,8 +425,8 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
/* Reserve bits before build-up */
fabric_bitstream.set_use_address(true);
fabric_bitstream.set_use_wl_address(true);
fabric_bitstream.set_bl_address_length(bl_port_info.get_width());
fabric_bitstream.set_wl_address_length(wl_port_info.get_width());
fabric_bitstream.set_bl_address_length(bl_addr_port_info.get_width());
fabric_bitstream.set_wl_address_length(wl_addr_port_info.get_width());
fabric_bitstream.reserve_bits(bitstream_manager.num_bits());
rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, top_block,