riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog

This commit is contained in:
tangxifan 2021-06-04 16:45:00 -06:00
parent 6e69c2d70a
commit d98be9f87b
4 changed files with 2 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -359,7 +359,6 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
/* Add Icarus requirement */
print_verilog_timeout_and_vcd(fp,
std::string(ICARUS_SIMULATOR_FLAG),
std::string(circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX)),
std::string(circuit_name + std::string("_formal.vcd")),
std::string(FORMAL_TB_SIM_START_PORT_NAME),

11
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -300,7 +300,6 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
* Note that: these codes are tuned for Icarus simulator!!!
*******************************************************************/
void print_verilog_timeout_and_vcd(std::fstream& fp,
const std::string& icarus_preprocessing_flag,
const std::string& module_name,
const std::string& vcd_fname,
const std::string& simulation_start_counter_name,
@ -309,20 +308,14 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
/* Validate the file stream */
valid_file_stream(fp);
/* The following verilog codes are tuned for Icarus */
print_verilog_preprocessing_flag(fp, icarus_preprocessing_flag);
print_verilog_comment(fp, std::string("----- Begin Icarus requirement -------"));
print_verilog_comment(fp, std::string("----- Begin output waveform to VCD file-------"));
fp << "\tinitial begin" << std::endl;
fp << "\t\t$dumpfile(\"" << vcd_fname << "\");" << std::endl;
fp << "\t\t$dumpvars(1, " << module_name << ");" << std::endl;
fp << "\tend" << std::endl;
/* Condition ends for the Icarus requirement */
print_verilog_endif(fp);
print_verilog_comment(fp, std::string("----- END Icarus requirement -------"));
print_verilog_comment(fp, std::string("----- END output waveform to VCD file -------"));
/* Add an empty line as splitter */
fp << std::endl;

1
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -55,7 +55,6 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const size_t& unused_io_value);
void print_verilog_timeout_and_vcd(std::fstream& fp,
const std::string& icarus_preprocessing_flag,
const std::string& module_name,
const std::string& vcd_fname,
const std::string& simulation_start_counter_name,

2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2496,7 +2496,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
* Always ceil the simulation time so that we test a sufficient length of period!!!
*/
print_verilog_timeout_and_vcd(fp,
std::string(ICARUS_SIMULATOR_FLAG),
std::string(circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX)),
std::string(circuit_name + std::string("_formal.vcd")),
std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
@ -2758,7 +2757,6 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
* Always ceil the simulation time so that we test a sufficient length of period!!!
*/
print_verilog_timeout_and_vcd(fp,
std::string(ICARUS_SIMULATOR_FLAG),
std::string(circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX)),
std::string(circuit_name + std::string("_formal.vcd")),
std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),