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[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions

This commit is contained in:
tangxifan 2021-06-29 14:26:33 -06:00
parent d0670e64d4
commit 77dddaeb39
8 changed files with 96 additions and 70 deletions
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16
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -192,10 +192,10 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager,
options);
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
print_verilog_full_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
return status;
}
@ -286,10 +286,10 @@ int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager,
options);
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
print_verilog_preconfigured_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
return status;
}

92
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -90,14 +90,14 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
/********************************************************************
* Print a file that includes all the netlists
* including the fabric netlists and testbenches
* including the fabric netlists and full testbenches
* that have been generated and user-defined.
* Some netlists are open to compile under specific preprocessing flags
*******************************************************************/
void print_verilog_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file) {
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
/* Create the file stream */
@ -132,28 +132,62 @@ void print_verilog_testbench_include_netlists(const std::string& src_dir,
print_verilog_endif(fp);
fp << std::endl;
/* Include formal verification netlists only when formal verification flag is enable */
print_verilog_preprocessing_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG));
/* Include top-level testbench only when auto-check flag is enabled */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
/* Close the file stream */
fp.close();
}
/********************************************************************
* Print a file that includes all the netlists
* including the fabric netlists and preconfigured testbenches
* that have been generated and user-defined.
* Some netlists are open to compile under specific preprocessing flags
*******************************************************************/
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
/* Validate the file stream */
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
/* Print preprocessing flags */
print_verilog_comment(fp, std::string("------ Include simulation defines -----"));
print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME));
fp << std::endl;
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
if (true == fabric_netlist_file.empty()) {
print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME));
} else {
VTR_ASSERT_SAFE(false == fabric_netlist_file.empty());
print_verilog_include_netlist(fp, fabric_netlist_file);
}
fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
fp << "\t";
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX));
/* Include formal verification testbench only when formal simulation flag is enabled */
fp << "\t";
print_verilog_preprocessing_flag(fp, std::string(FORMAL_SIMULATION_FLAG));
fp << "\t\t";
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
fp << "\t";
print_verilog_endif(fp);
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
print_verilog_endif(fp);
fp << std::endl;
/* Include top-level testbench only when auto-check flag is enabled */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
fp << "\t";
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
print_verilog_endif(fp);
fp << std::endl;
/* Include formal verification netlists */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX));
/* Include formal verification testbench */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
/* Close the file stream */
fp.close();
@ -213,18 +247,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
fp << std::endl;
}
/* To enable pre-configured FPGA simulation */
if (true == verilog_testbench_opts.print_formal_verification_top_netlist()) {
print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1);
fp << std::endl;
}
/* To enable pre-configured FPGA simulation */
if (true == verilog_testbench_opts.print_preconfig_top_testbench()) {
print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1);
fp << std::endl;
}
/* Close the file stream */
fp.close();
}

13
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
View File

@ -21,10 +21,15 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
const std::string& src_dir,
const CircuitLibrary& circuit_lib);
void print_verilog_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file);
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file);
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file);
void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
const FabricVerilogOption& fabric_verilog_opts);

2
openfpga/src/fpga_verilog/verilog_constants.h
View File

@ -7,9 +7,7 @@ constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v";
constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns
constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation
constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification
constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";

3
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -493,7 +493,8 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME),
circuit_lib,
module_manager,
top_module);
top_module,
false);
}
/* Testbench ends*/

34
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -791,7 +791,8 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
const std::vector<CircuitPortId>& circuit_input_ports,
const ModuleManager& module_manager,
const ModuleId& parent_module,
const ModuleId& primitive_module) {
const ModuleId& primitive_module,
const bool& deposit_random_values) {
/* Validate the file stream */
valid_file_stream(fp);
@ -819,7 +820,8 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
child_hie_path,
circuit_lib, circuit_model, circuit_input_ports,
module_manager, child_module,
primitive_module);
primitive_module,
deposit_random_values);
} else {
/* If the child module is the primitive module,
* we output the signal initialization codes for the input ports
@ -828,7 +830,6 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----"));
fp << "\tinitial begin" << std::endl;
fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl;
for (const auto& input_port : circuit_input_ports) {
/* Only for formal verification: deposite a zero signal values */
@ -838,22 +839,17 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
fp << "\t\t$deposit(";
fp << child_hie_path << ".";
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info, false);
fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0');
fp << ");" << std::endl;
}
fp << "\t`else" << std::endl;
if (!deposit_random_values) {
/* Regular case: deposite initial signal values: a random value */
for (const auto& input_port : circuit_input_ports) {
BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
input_port_info.set_origin_port_width(input_port_info.get_width());
fp << "\t\t$deposit(";
fp << child_hie_path << ".";
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info, false);
fp << ", $random % 2 ? 1'b1 : 1'b0);" << std::endl;
fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0');
fp << ");" << std::endl;
} else {
VTR_ASSERT_SAFE(deposit_random_values);
fp << ", $random % 2 ? 1'b1 : 1'b0);" << std::endl;
}
}
fp << "\t`endif\n" << std::endl;
fp << "\tend" << std::endl;
print_verilog_comment(fp, std::string("------ END driver initialization -----"));
}
@ -871,7 +867,8 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
const std::string& top_instance_name,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,
const ModuleId& top_module) {
const ModuleId& top_module,
const bool& deposit_random_values) {
/* Validate the file stream */
valid_file_stream(fp);
@ -921,7 +918,8 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
top_instance_name,
circuit_lib, signal_init_circuit_model, signal_init_circuit_ports.at(signal_init_circuit_model),
module_manager, top_module,
primitive_module);
primitive_module,
deposit_random_values);
}
}

3
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -101,7 +101,8 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
const std::string& top_instance_name,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,
const ModuleId& top_module);
const ModuleId& top_module,
const bool& deposit_random_values);
} /* end namespace openfpga */

3
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2029,7 +2029,8 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
circuit_lib,
module_manager,
top_module);
top_module,
true);
}