add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
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@ -744,19 +744,6 @@ std::string generate_sram_port_name(const e_config_protocol_type& sram_orgz_type
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std::string port_name;
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switch (sram_orgz_type) {
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case CONFIG_MEM_STANDALONE: {
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/* Two types of ports are available:
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* (1) Regular output of a SRAM, enabled by port type of INPUT
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* (2) Inverted output of a SRAM, enabled by port type of OUTPUT
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*/
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if (CIRCUIT_MODEL_PORT_INPUT == port_type) {
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port_name = std::string("mem_out");
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} else {
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VTR_ASSERT( CIRCUIT_MODEL_PORT_OUTPUT == port_type );
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port_name = std::string("mem_outb");
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}
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break;
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}
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case CONFIG_MEM_SCAN_CHAIN:
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/* Two types of ports are available:
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* (1) Head of a chain of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT
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@ -772,30 +759,25 @@ std::string generate_sram_port_name(const e_config_protocol_type& sram_orgz_type
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port_name = std::string("ccff_tail");
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}
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break;
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case CONFIG_MEM_STANDALONE:
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case CONFIG_MEM_MEMORY_BANK:
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/* Four types of ports are available:
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/* Two types of ports are available:
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* (1) Bit Lines (BLs) of a SRAM cell, enabled by port type of BL
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* (2) Word Lines (WLs) of a SRAM cell, enabled by port type of WL
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* (3) Inverted Bit Lines (BLBs) of a SRAM cell, enabled by port type of BLB
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* (4) Inverted Word Lines (WLBs) of a SRAM cell, enabled by port type of WLB
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*
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* BL BLB WL WLB BL BLB WL WLB BL BLB WL WLB
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* [0] [0] [0] [0] [1] [1] [1] [1] [i] [i] [i] [i]
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* ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
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* | | | | | | | | | | | |
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* BL WL BL WL BL WL
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* [0] [0] [1] [1] [i] [i]
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* ^ ^ ^ ^ ^ ^
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* | | | | | |
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* +----------+ +----------+ +----------+
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* | SRAM | | SRAM | ... | SRAM |
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* +----------+ +----------+ +----------+
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*/
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if (CIRCUIT_MODEL_PORT_BL == port_type) {
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port_name = std::string("bl");
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} else if (CIRCUIT_MODEL_PORT_WL == port_type) {
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port_name = std::string("wl");
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} else if (CIRCUIT_MODEL_PORT_BLB == port_type) {
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port_name = std::string("blb");
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port_name = std::string(MEMORY_BL_PORT_NAME);
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} else {
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VTR_ASSERT( CIRCUIT_MODEL_PORT_WLB == port_type );
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port_name = std::string("wlb");
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VTR_ASSERT( CIRCUIT_MODEL_PORT_WL == port_type );
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port_name = std::string(MEMORY_WL_PORT_NAME);
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}
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break;
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case CONFIG_MEM_FRAME_BASED:
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@ -314,20 +314,15 @@ std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_
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std::vector<e_circuit_model_port_type> model_port_types;
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switch (sram_orgz_type) {
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case CONFIG_MEM_STANDALONE:
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model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
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model_port_types.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
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break;
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case CONFIG_MEM_SCAN_CHAIN:
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model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
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model_port_types.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
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break;
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case CONFIG_MEM_STANDALONE:
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case CONFIG_MEM_MEMORY_BANK: {
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std::vector<e_circuit_model_port_type> ports_to_search;
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ports_to_search.push_back(CIRCUIT_MODEL_PORT_BL);
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ports_to_search.push_back(CIRCUIT_MODEL_PORT_WL);
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ports_to_search.push_back(CIRCUIT_MODEL_PORT_BLB);
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ports_to_search.push_back(CIRCUIT_MODEL_PORT_WLB);
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/* Try to find a BL/WL/BLB/WLB port and update the port types/module port types to be added */
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for (const auto& port_to_search : ports_to_search) {
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std::vector<CircuitPortId> found_port = circuit_lib.model_ports_by_type(sram_model, port_to_search);
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@ -664,6 +664,85 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
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}
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}
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/********************************************************************
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* Connect all the memory modules under the parent module in a flatten way
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*
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* BL
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* |
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* +---------------+--------- ... --------+
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* | | |
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* v v v
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* +--------+ +--------+ +--------+
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* | Memory | | Memory | ... | Memory |
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* | Module | | Module | | Module |
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* | [0] | | [1] | | [N-1] |
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* +--------+ +--------+ +--------+
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* ^ ^ ^
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* | | |
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* +------------+----------------------+
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* |
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* WL
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*
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* Note:
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* - This function will do the connection for only one type of the port,
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* either BL or WL. So, you should call this function twice to complete
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* the configuration bus connection!!!
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*
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*********************************************************************/
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void add_module_nets_cmos_flatten_memory_config_bus(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type,
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const e_circuit_model_port_type& config_port_type) {
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/* A counter for the current pin id for the source port of parent module */
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size_t cur_src_pin_id = 0;
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ModuleId net_src_module_id;
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size_t net_src_instance_id;
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ModulePortId net_src_port_id;
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/* Find the port name of parent module */
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std::string src_port_name = generate_sram_port_name(sram_orgz_type, config_port_type);
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net_src_module_id = parent_module;
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net_src_instance_id = 0;
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net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
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/* Get the pin id for source port */
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BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id);
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for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
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ModuleId net_sink_module_id;
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size_t net_sink_instance_id;
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ModulePortId net_sink_port_id;
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/* Find the port name of next memory module */
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std::string sink_port_name = generate_sram_port_name(sram_orgz_type, config_port_type);
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net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index];
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net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
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net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
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/* Get the pin id for sink port */
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BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id);
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < net_sink_port.pins().size(); ++pin_id) {
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/* Create a net and add source and sink to it */
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ModuleNetId net = create_module_source_pin_net(module_manager, parent_module,
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net_src_module_id, net_src_instance_id,
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net_src_port_id, net_src_port.pins()[cur_src_pin_id]);
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VTR_ASSERT(ModuleNetId::INVALID() != net);
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/* Add net sink */
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module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
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/* Move to the next src pin */
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cur_src_pin_id++;
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}
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}
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/* We should used all the pins of the source port!!! */
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VTR_ASSERT(net_src_port.get_width() == cur_src_pin_id);
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}
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/********************************************************************
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* Connect all the memory modules under the parent module in a chain
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*
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@ -1088,18 +1167,19 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type) {
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switch (sram_orgz_type) {
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case CONFIG_MEM_STANDALONE:
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/* Nothing to do */
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break;
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case CONFIG_MEM_SCAN_CHAIN: {
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add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, sram_orgz_type);
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add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module,
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sram_orgz_type);
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break;
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}
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case CONFIG_MEM_STANDALONE:
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case CONFIG_MEM_MEMORY_BANK:
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/* TODO: */
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add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
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sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
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add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
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sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
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break;
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case CONFIG_MEM_FRAME_BASED:
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/* TODO: */
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add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
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break;
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default:
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@ -1557,6 +1637,32 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
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return num_config_bits;
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}
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/********************************************************************
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* Try to create a net for the source pin
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* This function will try
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* - Find if there is already a net created whose source is the pin
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* If so, it will return the net id
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* - If not, it will create a net and configure its source
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*******************************************************************/
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ModuleNetId create_module_source_pin_net(ModuleManager& module_manager,
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const ModuleId& cur_module_id,
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const ModuleId& src_module_id,
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const size_t& src_instance_id,
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const ModulePortId& src_module_port_id,
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const size_t& src_pin_id) {
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ModuleNetId net = module_manager.module_instance_port_net(cur_module_id,
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src_module_id, src_instance_id,
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src_module_port_id, src_pin_id);
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if (ModuleNetId::INVALID() == net) {
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net = module_manager.create_module_net(cur_module_id);
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module_manager.add_module_net_source(cur_module_id, net,
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src_module_id, src_instance_id,
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src_module_port_id, src_pin_id);
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}
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return net;
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}
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/********************************************************************
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* Add a bus of nets to a module (cur_module_id)
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* Note:
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@ -1609,14 +1715,11 @@ void add_module_bus_nets(ModuleManager& module_manager,
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) {
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ModuleNetId net = module_manager.module_instance_port_net(cur_module_id,
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src_module_id, src_instance_id,
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src_module_port_id, src_port.pins()[pin_id]);
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if (ModuleNetId::INVALID() == net) {
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net = module_manager.create_module_net(cur_module_id);
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/* Configure the net source */
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module_manager.add_module_net_source(cur_module_id, net, src_module_id, src_instance_id, src_module_port_id, src_port.pins()[pin_id]);
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}
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ModuleNetId net = create_module_source_pin_net(module_manager, cur_module_id,
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src_module_id, src_instance_id,
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src_module_port_id, src_port.pins()[pin_id]);
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VTR_ASSERT(ModuleNetId::INVALID() != net);
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/* Configure the net sink */
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module_manager.add_module_net_sink(cur_module_id, net, des_module_id, des_instance_id, des_module_port_id, des_port.pins()[pin_id]);
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}
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@ -91,6 +91,11 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& logic_model);
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void add_module_nets_cmos_flatten_memory_config_bus(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type,
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const e_circuit_model_port_type& config_port_type);
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void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type);
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@ -135,6 +140,13 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
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const CircuitModelId& sram_model,
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const e_config_protocol_type& sram_orgz_type);
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ModuleNetId create_module_source_pin_net(ModuleManager& module_manager,
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const ModuleId& cur_module_id,
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const ModuleId& src_module_id,
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const size_t& src_instance_id,
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const ModulePortId& src_module_port_id,
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const size_t& src_pin_id);
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void add_module_bus_nets(ModuleManager& module_manager,
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const ModuleId& cur_module_id,
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const ModuleId& src_module_id,
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