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add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)

This commit is contained in:
tangxifan 2020-05-29 22:41:56 -06:00
parent d2d443a988
commit fbe05963e0
4 changed files with 139 additions and 47 deletions
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36
openfpga/src/base/openfpga_naming.cpp
View File

@ -744,19 +744,6 @@ std::string generate_sram_port_name(const e_config_protocol_type& sram_orgz_type
std::string port_name;
switch (sram_orgz_type) {
case CONFIG_MEM_STANDALONE: {
/* Two types of ports are available:
* (1) Regular output of a SRAM, enabled by port type of INPUT
* (2) Inverted output of a SRAM, enabled by port type of OUTPUT
*/
if (CIRCUIT_MODEL_PORT_INPUT == port_type) {
port_name = std::string("mem_out");
} else {
VTR_ASSERT( CIRCUIT_MODEL_PORT_OUTPUT == port_type );
port_name = std::string("mem_outb");
}
break;
}
case CONFIG_MEM_SCAN_CHAIN:
/* Two types of ports are available:
* (1) Head of a chain of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT
@ -772,30 +759,25 @@ std::string generate_sram_port_name(const e_config_protocol_type& sram_orgz_type
port_name = std::string("ccff_tail");
}
break;
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_MEMORY_BANK:
/* Four types of ports are available:
/* Two types of ports are available:
* (1) Bit Lines (BLs) of a SRAM cell, enabled by port type of BL
* (2) Word Lines (WLs) of a SRAM cell, enabled by port type of WL
* (3) Inverted Bit Lines (BLBs) of a SRAM cell, enabled by port type of BLB
* (4) Inverted Word Lines (WLBs) of a SRAM cell, enabled by port type of WLB
*
* BL BLB WL WLB BL BLB WL WLB BL BLB WL WLB
* [0] [0] [0] [0] [1] [1] [1] [1] [i] [i] [i] [i]
* ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
* | | | | | | | | | | | |
* BL WL BL WL BL WL
* [0] [0] [1] [1] [i] [i]
* ^ ^ ^ ^ ^ ^
* | | | | | |
* +----------+ +----------+ +----------+
* | SRAM | | SRAM | ... | SRAM |
* +----------+ +----------+ +----------+
*/
if (CIRCUIT_MODEL_PORT_BL == port_type) {
port_name = std::string("bl");
} else if (CIRCUIT_MODEL_PORT_WL == port_type) {
port_name = std::string("wl");
} else if (CIRCUIT_MODEL_PORT_BLB == port_type) {
port_name = std::string("blb");
port_name = std::string(MEMORY_BL_PORT_NAME);
} else {
VTR_ASSERT( CIRCUIT_MODEL_PORT_WLB == port_type );
port_name = std::string("wlb");
VTR_ASSERT( CIRCUIT_MODEL_PORT_WL == port_type );
port_name = std::string(MEMORY_WL_PORT_NAME);
}
break;
case CONFIG_MEM_FRAME_BASED:

7
openfpga/src/utils/memory_utils.cpp
View File

@ -314,20 +314,15 @@ std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_
std::vector<e_circuit_model_port_type> model_port_types;
switch (sram_orgz_type) {
case CONFIG_MEM_STANDALONE:
model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
model_port_types.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
break;
case CONFIG_MEM_SCAN_CHAIN:
model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
model_port_types.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
break;
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_MEMORY_BANK: {
std::vector<e_circuit_model_port_type> ports_to_search;
ports_to_search.push_back(CIRCUIT_MODEL_PORT_BL);
ports_to_search.push_back(CIRCUIT_MODEL_PORT_WL);
ports_to_search.push_back(CIRCUIT_MODEL_PORT_BLB);
ports_to_search.push_back(CIRCUIT_MODEL_PORT_WLB);
/* Try to find a BL/WL/BLB/WLB port and update the port types/module port types to be added */
for (const auto& port_to_search : ports_to_search) {
std::vector<CircuitPortId> found_port = circuit_lib.model_ports_by_type(sram_model, port_to_search);

131
openfpga/src/utils/module_manager_utils.cpp
View File

@ -664,6 +664,85 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
}
}
/********************************************************************
* Connect all the memory modules under the parent module in a flatten way
*
* BL
* |
* +---------------+--------- ... --------+
* | | |
* v v v
* +--------+ +--------+ +--------+
* | Memory | | Memory | ... | Memory |
* | Module | | Module | | Module |
* | [0] | | [1] | | [N-1] |
* +--------+ +--------+ +--------+
* ^ ^ ^
* | | |
* +------------+----------------------+
* |
* WL
*
* Note:
* - This function will do the connection for only one type of the port,
* either BL or WL. So, you should call this function twice to complete
* the configuration bus connection!!!
*
*********************************************************************/
void add_module_nets_cmos_flatten_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_port_type& config_port_type) {
/* A counter for the current pin id for the source port of parent module */
size_t cur_src_pin_id = 0;
ModuleId net_src_module_id;
size_t net_src_instance_id;
ModulePortId net_src_port_id;
/* Find the port name of parent module */
std::string src_port_name = generate_sram_port_name(sram_orgz_type, config_port_type);
net_src_module_id = parent_module;
net_src_instance_id = 0;
net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
/* Get the pin id for source port */
BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id);
for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
ModuleId net_sink_module_id;
size_t net_sink_instance_id;
ModulePortId net_sink_port_id;
/* Find the port name of next memory module */
std::string sink_port_name = generate_sram_port_name(sram_orgz_type, config_port_type);
net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index];
net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
/* Get the pin id for sink port */
BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id);
/* Create a net for each pin */
for (size_t pin_id = 0; pin_id < net_sink_port.pins().size(); ++pin_id) {
/* Create a net and add source and sink to it */
ModuleNetId net = create_module_source_pin_net(module_manager, parent_module,
net_src_module_id, net_src_instance_id,
net_src_port_id, net_src_port.pins()[cur_src_pin_id]);
VTR_ASSERT(ModuleNetId::INVALID() != net);
/* Add net sink */
module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
/* Move to the next src pin */
cur_src_pin_id++;
}
}
/* We should used all the pins of the source port!!! */
VTR_ASSERT(net_src_port.get_width() == cur_src_pin_id);
}
/********************************************************************
* Connect all the memory modules under the parent module in a chain
*
@ -1088,18 +1167,19 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type) {
switch (sram_orgz_type) {
case CONFIG_MEM_STANDALONE:
/* Nothing to do */
break;
case CONFIG_MEM_SCAN_CHAIN: {
add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, sram_orgz_type);
add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module,
sram_orgz_type);
break;
}
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_MEMORY_BANK:
/* TODO: */
add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
break;
case CONFIG_MEM_FRAME_BASED:
/* TODO: */
add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
break;
default:
@ -1557,6 +1637,32 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
return num_config_bits;
}
/********************************************************************
* Try to create a net for the source pin
* This function will try
* - Find if there is already a net created whose source is the pin
* If so, it will return the net id
* - If not, it will create a net and configure its source
*******************************************************************/
ModuleNetId create_module_source_pin_net(ModuleManager& module_manager,
const ModuleId& cur_module_id,
const ModuleId& src_module_id,
const size_t& src_instance_id,
const ModulePortId& src_module_port_id,
const size_t& src_pin_id) {
ModuleNetId net = module_manager.module_instance_port_net(cur_module_id,
src_module_id, src_instance_id,
src_module_port_id, src_pin_id);
if (ModuleNetId::INVALID() == net) {
net = module_manager.create_module_net(cur_module_id);
module_manager.add_module_net_source(cur_module_id, net,
src_module_id, src_instance_id,
src_module_port_id, src_pin_id);
}
return net;
}
/********************************************************************
* Add a bus of nets to a module (cur_module_id)
* Note:
@ -1609,14 +1715,11 @@ void add_module_bus_nets(ModuleManager& module_manager,
/* Create a net for each pin */
for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) {
ModuleNetId net = module_manager.module_instance_port_net(cur_module_id,
src_module_id, src_instance_id,
src_module_port_id, src_port.pins()[pin_id]);
if (ModuleNetId::INVALID() == net) {
net = module_manager.create_module_net(cur_module_id);
/* Configure the net source */
module_manager.add_module_net_source(cur_module_id, net, src_module_id, src_instance_id, src_module_port_id, src_port.pins()[pin_id]);
}
ModuleNetId net = create_module_source_pin_net(module_manager, cur_module_id,
src_module_id, src_instance_id,
src_module_port_id, src_port.pins()[pin_id]);
VTR_ASSERT(ModuleNetId::INVALID() != net);
/* Configure the net sink */
module_manager.add_module_net_sink(cur_module_id, net, des_module_id, des_instance_id, des_module_port_id, des_port.pins()[pin_id]);
}

12
openfpga/src/utils/module_manager_utils.h
View File

@ -91,6 +91,11 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
const CircuitLibrary& circuit_lib,
const CircuitModelId& logic_model);
void add_module_nets_cmos_flatten_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type,
const e_circuit_model_port_type& config_port_type);
void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const e_config_protocol_type& sram_orgz_type);
@ -135,6 +140,13 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type);
ModuleNetId create_module_source_pin_net(ModuleManager& module_manager,
const ModuleId& cur_module_id,
const ModuleId& src_module_id,
const size_t& src_instance_id,
const ModulePortId& src_module_port_id,
const size_t& src_pin_id);
void add_module_bus_nets(ModuleManager& module_manager,
const ModuleId& cur_module_id,
const ModuleId& src_module_id,