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ignore invalid nets when decoding bitstream

This commit is contained in:
tangxifan 2020-06-16 22:26:36 -06:00
parent 9d0e002532
commit 19c0b57df6
2 changed files with 29 additions and 12 deletions
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4
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -159,11 +159,15 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag
/* Find the path id:
* - if des pb is not valid, this is an unmapped pb, we can set a default path_id
* - There is no net mapped to des_pb_graph_pin we use default path id
* - There is a net mapped to des_pin_graph_pin: we find the path id
*/
const PhysicalPbId& des_pb_id = physical_pb.find_pb(des_pb_graph_pin->parent_node);
size_t mux_input_pin_id = 0;
if (true != physical_pb.valid_pb_id(des_pb_id)) {
mux_input_pin_id = DEFAULT_PATH_ID;
} else if (AtomNetId::INVALID() == physical_pb.pb_graph_pin_atom_net(des_pb_id, des_pb_graph_pin)) {
mux_input_pin_id = DEFAULT_PATH_ID;
} else {
for (t_pb_graph_pin* src_pb_graph_pin : pb_graph_pin_inputs(des_pb_graph_pin, cur_interc)) {
const PhysicalPbId& src_pb_id = physical_pb.find_pb(src_pb_graph_pin->parent_node);

37
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -50,12 +50,18 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
/* Find the input size of the implementation of a routing multiplexer */
size_t datapath_mux_size = drive_rr_nodes.size();
/* Find out which routing path is used in this MUX */
/* Find out which routing path is used in this MUX
* Two conditions to be considered:
* - There is no net mapped to cur_rr_node: we use default path id
* - There is a net mapped to cur_rr_node: we find the path id
*/
int path_id = DEFAULT_PATH_ID;
for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) {
if (routing_annotation.rr_node_net(drive_rr_nodes[inode]) == routing_annotation.rr_node_net(cur_rr_node)) {
path_id = (int)inode;
break;
if (ClusterNetId::INVALID() != routing_annotation.rr_node_net(cur_rr_node)) {
for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) {
if (routing_annotation.rr_node_net(drive_rr_nodes[inode]) == routing_annotation.rr_node_net(cur_rr_node)) {
path_id = (int)inode;
break;
}
}
}
@ -205,13 +211,21 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
/* Configuration bits for MUX*/
int path_id = DEFAULT_PATH_ID;
int edge_index = 0;
for (const RREdgeId& edge : rr_graph.node_in_edges(src_rr_node)) {
RRNodeId driver_node = rr_graph.edge_src_node(edge);
if (routing_annotation.rr_node_net(driver_node) == routing_annotation.rr_node_net(src_rr_node)) {
path_id = edge_index;
break;
/* Find which path is connected to the output of this routing multiplexer
* Two conditions to be considered:
* - There is no net mapped to src_rr_node: we use default path id
* - There is a net mapped to src_rr_node: we find the path id
*/
if (ClusterNetId::INVALID() != routing_annotation.rr_node_net(src_rr_node)) {
for (const RREdgeId& edge : rr_graph.node_in_edges(src_rr_node)) {
RRNodeId driver_node = rr_graph.edge_src_node(edge);
if (routing_annotation.rr_node_net(driver_node) == routing_annotation.rr_node_net(src_rr_node)) {
path_id = edge_index;
break;
}
edge_index++;
}
edge_index++;
}
/* Ensure that our path id makes sense! */
@ -219,7 +233,6 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
|| ( (DEFAULT_PATH_ID < path_id) && (path_id < (int)datapath_mux_size) )
);
/* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */
std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(rr_graph, src_rr_node);
VTR_ASSERT(1 == driver_switches.size());