echo path in architecture bitstream database

openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp

@@ -82,7 +82,12 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp,
 
   /* Output child bits under this block */
   size_t bit_counter = 0;
-  fp << "\t<bitstream>" << std::endl;
+  fp << "\t<bitstream";
+  /* Output path id only when it is valid */
+  if (true == bitstream_manager.valid_block_path_id(block)) {
+    fp << " path_id=\"" << bitstream_manager.block_path_id(block) << "\"";
+  }
+  fp << ">" << std::endl;
   for (const ConfigBitId& child_bit : bitstream_manager.block_bits(block)) {
     fp << "\t\t<bit";
     fp << " memory_port=\"" << generate_configurable_memory_data_out_name() << "[" << bit_counter << "]" << "\"";

openfpga/src/fpga_bitstream/bitstream_manager.cpp

@@ -108,6 +108,13 @@ ConfigBlockId BitstreamManager::find_child_block(const ConfigBlockId& block_id,
   return candidates[0];
 }
 
+int BitstreamManager::block_path_id(const ConfigBlockId& block_id) const {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_block_id(block_id));
+
+  return block_path_ids_[block_id];
+}
+
 /******************************************************************************
  * Public Mutators
  ******************************************************************************/
@@ -128,6 +135,7 @@ ConfigBlockId BitstreamManager::add_block(const std::string& block_name) {
   block_ids_.push_back(block);
   block_names_.push_back(block_name);
   block_bit_ids_.emplace_back();
+  block_path_ids_.push_back(-2);
   parent_block_ids_.push_back(ConfigBlockId::INVALID());
   child_block_ids_.emplace_back();
 
@@ -166,6 +174,14 @@ void BitstreamManager::add_bit_to_block(const ConfigBlockId& block, const Config
   bit_parent_block_ids_[bit] = block;
 }
 
+void BitstreamManager::add_path_id_to_block(const ConfigBlockId& block, const int& path_id) {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_block_id(block));
+
+  /* Add the bit to the block */
+  block_path_ids_[block] = path_id;
+}
+
 void BitstreamManager::add_shared_config_bit_values(const ConfigBitId& bit, const std::vector<bool>& shared_config_bits) {
   /* Ensure the input ids are valid */
   VTR_ASSERT(true == valid_bit_id(bit));
@@ -184,4 +200,8 @@ bool BitstreamManager::valid_block_id(const ConfigBlockId& block_id) const {
   return (size_t(block_id) < block_ids_.size()) && (block_id == block_ids_[block_id]);
 }
 
+bool BitstreamManager::valid_block_path_id(const ConfigBlockId& block_id) const {
+  return (true == valid_block_id(block_id)) && (-2 != block_path_id(block_id));
+}
+
 } /* end namespace openfpga */

openfpga/src/fpga_bitstream/bitstream_manager.h

@@ -82,6 +82,9 @@ class BitstreamManager {
     /* Find the child block in a bitstream manager with a given name */
     ConfigBlockId find_child_block(const ConfigBlockId& block_id, const std::string& child_block_name) const;
 
+    /* Find path id of a block */
+    int block_path_id(const ConfigBlockId& block_id) const;
+
   public:  /* Public Mutators */
     /* Add a new configuration bit to the bitstream manager */
     ConfigBitId add_bit(const bool& bit_value);
@@ -95,6 +98,9 @@ class BitstreamManager {
     /* Add a configuration bit to a block */
     void add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit);
 
+    /* Add a path id to a block */
+    void add_path_id_to_block(const ConfigBlockId& block, const int& path_id);
+
     /* Add share configuration bits to a configuration bit */
     void add_shared_config_bit_values(const ConfigBitId& bit, const std::vector<bool>& shared_config_bits);
 
@@ -103,6 +109,8 @@ class BitstreamManager {
 
     bool valid_block_id(const ConfigBlockId& block_id) const;
 
+    bool valid_block_path_id(const ConfigBlockId& block_id) const;
+
   private: /* Internal data */
     /* Unique id of a block of bits in the Bitstream */
     vtr::vector<ConfigBlockId, ConfigBlockId> block_ids_; 
@@ -118,6 +126,7 @@ class BitstreamManager {
     vtr::vector<ConfigBlockId, std::string> block_names_; 
     vtr::vector<ConfigBlockId, ConfigBlockId> parent_block_ids_; 
     vtr::vector<ConfigBlockId, std::vector<ConfigBlockId>> child_block_ids_; 
+    vtr::vector<ConfigBlockId, int> block_path_ids_; 
 
     /* Unique id of a bit in the Bitstream */
     vtr::vector<ConfigBitId, ConfigBitId> bit_ids_; 

openfpga/src/fpga_bitstream/build_grid_bitstream.cpp

@@ -203,6 +203,8 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag
       /* Link the memory bits to the mux mem block */
       bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
     }
+    /* Record path ids */
+    bitstream_manager.add_path_id_to_block(mux_mem_block, mux_input_pin_id);
     break;
   }
   default:

openfpga/src/fpga_bitstream/build_routing_bitstream.cpp

@@ -85,6 +85,8 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
     /* Link the memory bits to the mux mem block */
     bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
   }
+  /* Record path ids */
+  bitstream_manager.add_path_id_to_block(mux_mem_block, path_id);
 }
 
 /********************************************************************
@@ -239,6 +241,8 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
     /* Link the memory bits to the mux mem block */
     bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
   }
+  /* Record path ids */
+  bitstream_manager.add_path_id_to_block(mux_mem_block, path_id);
 }