riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Engine] Bug fix in finding the start index of BL/WL for each column/row;

This commit is contained in:
tangxifan 2021-09-22 10:20:40 -07:00
parent 7db7e2d8f6
commit ad432e4d95
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
openfpga/src/utils/memory_bank_utils.cpp
View File

@ -123,7 +123,12 @@ std::map<int, size_t> compute_memory_bank_regional_blwl_start_index_per_tile(con
if (iblwl == child_xy_range.first) {
blwl_start_index_per_tile[iblwl] = 0;
} else {
blwl_start_index_per_tile[iblwl] = num_blwls_per_tile.at(iblwl - 1) + blwl_start_index_per_tile[iblwl - 1];
auto result = num_blwls_per_tile.find(iblwl - 1);
if (result == num_blwls_per_tile.end()) {
blwl_start_index_per_tile[iblwl] = blwl_start_index_per_tile[iblwl - 1];
} else {
blwl_start_index_per_tile[iblwl] = result->second + blwl_start_index_per_tile[iblwl - 1];
}
}
}
return blwl_start_index_per_tile;