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[Engine] Add check codes to validate circuit models for BL/WL protocols

This commit is contained in:
tangxifan 2021-09-23 14:39:16 -07:00
parent 6645b70ae3
commit 8c281a22b0
3 changed files with 40 additions and 14 deletions
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5
openfpga/src/base/openfpga_read_arch.cpp
View File

@ -56,9 +56,8 @@ int read_arch(OpenfpgaContext& openfpga_context,
return CMD_EXEC_FATAL_ERROR;
}
if (false == check_configurable_memory_circuit_model(openfpga_context.arch().config_protocol.type(),
openfpga_context.arch().circuit_lib,
openfpga_context.arch().config_protocol.memory_model())) {
if (false == check_configurable_memory_circuit_model(openfpga_context.arch().config_protocol,
openfpga_context.arch().circuit_lib)) {
return CMD_EXEC_FATAL_ERROR;
}

42
openfpga/src/utils/circuit_library_utils.cpp
View File

@ -280,22 +280,50 @@ std::vector<std::string> find_circuit_library_unique_spice_netlists(const Circui
* Advanced check if the circuit model of configurable memory
* satisfy the needs of configuration protocol
* - Configuration chain -based: we check if we have a CCFF model
* - Frame -based: we check if we have a SRAM model which has BL and WL
*
* - Flatten/Frame -based: we check if we have a SRAM model which has BL and WL
* - Memory bank: we check if we have a SRAM model. Also we need to check if we have valid CCFF models for BL/WL models (if selected)
***********************************************************************/
bool check_configurable_memory_circuit_model(const e_config_protocol_type& config_protocol_type,
const CircuitLibrary& circuit_lib,
const CircuitModelId& config_mem_circuit_model) {
bool check_configurable_memory_circuit_model(const ConfigProtocol& config_protocol,
const CircuitLibrary& circuit_lib) {
size_t num_err = 0;
CircuitModelId config_mem_circuit_model = config_protocol.memory_model();
switch (config_protocol_type) {
switch (config_protocol.type()) {
case CONFIG_MEM_SCAN_CHAIN:
num_err = check_ccff_circuit_model_ports(circuit_lib,
config_mem_circuit_model);
break;
case CONFIG_MEM_QL_MEMORY_BANK: {
num_err = check_sram_circuit_model_ports(circuit_lib,
config_mem_circuit_model,
true);
/* Check circuit model for BL protocol */
CircuitModelId bl_memory_model = config_protocol.bl_memory_model();
if ( BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()
&& CircuitModelId::INVALID() == bl_memory_model) {
VTR_LOG_ERROR("Expect a valid CCFF circuit model for BL protocol");
num_err++;
}
if (bl_memory_model) {
num_err += check_ccff_circuit_model_ports(circuit_lib,
bl_memory_model);
}
/* Check circuit model for WL protocol */
CircuitModelId wl_memory_model = config_protocol.wl_memory_model();
if ( BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type()
&& CircuitModelId::INVALID() == wl_memory_model) {
VTR_LOG_ERROR("Expect a valid CCFF circuit model for WL protocol");
num_err++;
}
if (wl_memory_model) {
num_err += check_ccff_circuit_model_ports(circuit_lib,
wl_memory_model);
}
break;
}
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_MEMORY_BANK:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_FRAME_BASED:
num_err = check_sram_circuit_model_ports(circuit_lib,
config_mem_circuit_model,

7
openfpga/src/utils/circuit_library_utils.h
View File

@ -8,8 +8,8 @@
* Include header files that are required by function declaration
*******************************************************************/
#include <vector>
#include "circuit_types.h"
#include "circuit_library.h"
#include "config_protocol.h"
/********************************************************************
* Function declaration
@ -41,9 +41,8 @@ std::vector<std::string> find_circuit_library_unique_verilog_netlists(const Circ
std::vector<std::string> find_circuit_library_unique_spice_netlists(const CircuitLibrary& circuit_lib);
bool check_configurable_memory_circuit_model(const e_config_protocol_type& config_protocol_type,
const CircuitLibrary& circuit_lib,
const CircuitModelId& config_mem_circuit_model);
bool check_configurable_memory_circuit_model(const ConfigProtocol& config_protocol,
const CircuitLibrary& circuit_lib);
CircuitPortId find_circuit_model_power_gate_en_port(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);