From 8c281a22b09a8ab2ef410147acc4afb727420a74 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Sep 2021 14:39:16 -0700
Subject: [PATCH] [Engine] Add check codes to validate circuit models for BL/WL
 protocols

---
 openfpga/src/base/openfpga_read_arch.cpp     |  5 +--
 openfpga/src/utils/circuit_library_utils.cpp | 42 ++++++++++++++++----
 openfpga/src/utils/circuit_library_utils.h   |  7 ++--
 3 files changed, 40 insertions(+), 14 deletions(-)

diff --git a/openfpga/src/base/openfpga_read_arch.cpp b/openfpga/src/base/openfpga_read_arch.cpp
index 25bfc3831..56d96f740 100644
--- a/openfpga/src/base/openfpga_read_arch.cpp
+++ b/openfpga/src/base/openfpga_read_arch.cpp
@@ -56,9 +56,8 @@ int read_arch(OpenfpgaContext& openfpga_context,
     return CMD_EXEC_FATAL_ERROR;
   }
 
-  if (false == check_configurable_memory_circuit_model(openfpga_context.arch().config_protocol.type(),
-                                                       openfpga_context.arch().circuit_lib,
-                                                       openfpga_context.arch().config_protocol.memory_model())) {
+  if (false == check_configurable_memory_circuit_model(openfpga_context.arch().config_protocol,
+                                                       openfpga_context.arch().circuit_lib)) {
     return CMD_EXEC_FATAL_ERROR;
   }
 
diff --git a/openfpga/src/utils/circuit_library_utils.cpp b/openfpga/src/utils/circuit_library_utils.cpp
index fabdc05da..bb59a0601 100644
--- a/openfpga/src/utils/circuit_library_utils.cpp
+++ b/openfpga/src/utils/circuit_library_utils.cpp
@@ -280,22 +280,50 @@ std::vector<std::string> find_circuit_library_unique_spice_netlists(const Circui
  * Advanced check if the circuit model of configurable memory
  * satisfy the needs of configuration protocol
  * - Configuration chain -based: we check if we have a CCFF model
- * - Frame -based: we check if we have a SRAM model which has BL and WL
- * 
+ * - Flatten/Frame -based: we check if we have a SRAM model which has BL and WL
+ * - Memory bank: we check if we have a SRAM model. Also we need to check if we have valid CCFF models for BL/WL models (if selected)
  ***********************************************************************/
-bool check_configurable_memory_circuit_model(const e_config_protocol_type& config_protocol_type,
-                                             const CircuitLibrary& circuit_lib,
-                                             const CircuitModelId& config_mem_circuit_model) {
+bool check_configurable_memory_circuit_model(const ConfigProtocol& config_protocol,
+                                             const CircuitLibrary& circuit_lib) {
   size_t num_err = 0;
+  CircuitModelId config_mem_circuit_model = config_protocol.memory_model();
 
-  switch (config_protocol_type) {
+  switch (config_protocol.type()) {
   case CONFIG_MEM_SCAN_CHAIN:   
     num_err = check_ccff_circuit_model_ports(circuit_lib,
                                              config_mem_circuit_model);
     break;
+  case CONFIG_MEM_QL_MEMORY_BANK: {
+    num_err = check_sram_circuit_model_ports(circuit_lib,
+                                             config_mem_circuit_model,
+                                             true);
+    /* Check circuit model for BL protocol */ 
+    CircuitModelId bl_memory_model = config_protocol.bl_memory_model();
+    if ( BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()
+      && CircuitModelId::INVALID() == bl_memory_model) { 
+      VTR_LOG_ERROR("Expect a valid CCFF circuit model for BL protocol");
+      num_err++;
+    }
+    if (bl_memory_model) { 
+      num_err += check_ccff_circuit_model_ports(circuit_lib,
+                                                bl_memory_model);
+    }
+
+    /* Check circuit model for WL protocol */ 
+    CircuitModelId wl_memory_model = config_protocol.wl_memory_model();
+    if ( BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.wl_protocol_type()
+      && CircuitModelId::INVALID() == wl_memory_model) { 
+      VTR_LOG_ERROR("Expect a valid CCFF circuit model for WL protocol");
+      num_err++;
+    }
+    if (wl_memory_model) { 
+      num_err += check_ccff_circuit_model_ports(circuit_lib,
+                                                wl_memory_model);
+    }
+    break;
+  }
   case CONFIG_MEM_STANDALONE: 
   case CONFIG_MEM_MEMORY_BANK:  
-  case CONFIG_MEM_QL_MEMORY_BANK:  
   case CONFIG_MEM_FRAME_BASED:  
     num_err = check_sram_circuit_model_ports(circuit_lib,
                                              config_mem_circuit_model,
diff --git a/openfpga/src/utils/circuit_library_utils.h b/openfpga/src/utils/circuit_library_utils.h
index 758af9689..fe5fb03f7 100644
--- a/openfpga/src/utils/circuit_library_utils.h
+++ b/openfpga/src/utils/circuit_library_utils.h
@@ -8,8 +8,8 @@
  * Include header files that are required by function declaration
  *******************************************************************/
 #include <vector>
-#include "circuit_types.h"
 #include "circuit_library.h"
+#include "config_protocol.h"
 
 /********************************************************************
  * Function declaration
@@ -41,9 +41,8 @@ std::vector<std::string> find_circuit_library_unique_verilog_netlists(const Circ
 
 std::vector<std::string> find_circuit_library_unique_spice_netlists(const CircuitLibrary& circuit_lib);
 
-bool check_configurable_memory_circuit_model(const e_config_protocol_type& config_protocol_type,
-                                             const CircuitLibrary& circuit_lib,
-                                             const CircuitModelId& config_mem_circuit_model);
+bool check_configurable_memory_circuit_model(const ConfigProtocol& config_protocol,
+                                             const CircuitLibrary& circuit_lib);
 
 CircuitPortId find_circuit_model_power_gate_en_port(const CircuitLibrary& circuit_lib,
                                                     const CircuitModelId& circuit_model);