riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Engine] Upgrade parser to support BL/WL protocols

This commit is contained in:
tangxifan 2021-09-23 14:25:25 -07:00
parent d4e3445153
commit 6645b70ae3
4 changed files with 200 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

73
libopenfpga/libarchopenfpga/src/config_protocol.cpp
View File

@ -1,4 +1,5 @@
#include "vtr_assert.h"
#include "vtr_log.h"
#include "config_protocol.h"
@ -32,6 +33,30 @@ int ConfigProtocol::num_regions() const {
return num_regions_;
}
e_blwl_protocol_type ConfigProtocol::bl_protocol_type() const {
return bl_protocol_type_;
}
std::string ConfigProtocol::bl_memory_model_name() const {
return bl_memory_model_name_;
}
CircuitModelId ConfigProtocol::bl_memory_model() const {
return bl_memory_model_;
}
e_blwl_protocol_type ConfigProtocol::wl_protocol_type() const {
return wl_protocol_type_;
}
std::string ConfigProtocol::wl_memory_model_name() const {
return wl_memory_model_name_;
}
CircuitModelId ConfigProtocol::wl_memory_model() const {
return wl_memory_model_;
}
/************************************************************************
* Public Mutators
***********************************************************************/
@ -50,3 +75,51 @@ void ConfigProtocol::set_memory_model(const CircuitModelId& memory_model) {
void ConfigProtocol::set_num_regions(const int& num_regions) {
num_regions_ = num_regions;
}
void ConfigProtocol::set_bl_protocol_type(const e_blwl_protocol_type& type) {
if (CONFIG_MEM_QL_MEMORY_BANK != type_) {
VTR_LOG_ERROR("BL protocol type is only applicable for configuration protocol '%d'", CONFIG_PROTOCOL_TYPE_STRING[type_]);
return;
}
bl_protocol_type_ = type;
}
void ConfigProtocol::set_bl_memory_model_name(const std::string& memory_model_name) {
if (BLWL_PROTOCOL_SHIFT_REGISTER != bl_protocol_type_) {
VTR_LOG_ERROR("BL protocol memory model is only applicable when '%d' is defined", BLWL_PROTOCOL_TYPE_STRING[bl_protocol_type_]);
return;
}
bl_memory_model_name_ = memory_model_name;
}
void ConfigProtocol::set_bl_memory_model(const CircuitModelId& memory_model) {
if (BLWL_PROTOCOL_SHIFT_REGISTER != bl_protocol_type_) {
VTR_LOG_ERROR("BL protocol memory model is only applicable when '%d' is defined", BLWL_PROTOCOL_TYPE_STRING[bl_protocol_type_]);
return;
}
bl_memory_model_ = memory_model;
}
void ConfigProtocol::set_wl_protocol_type(const e_blwl_protocol_type& type) {
if (CONFIG_MEM_QL_MEMORY_BANK != type_) {
VTR_LOG_ERROR("WL protocol type is only applicable for configuration protocol '%d'", CONFIG_PROTOCOL_TYPE_STRING[type_]);
return;
}
wl_protocol_type_ = type;
}
void ConfigProtocol::set_wl_memory_model_name(const std::string& memory_model_name) {
if (BLWL_PROTOCOL_SHIFT_REGISTER != wl_protocol_type_) {
VTR_LOG_ERROR("WL protocol memory model is only applicable when '%d' is defined", BLWL_PROTOCOL_TYPE_STRING[wl_protocol_type_]);
return;
}
wl_memory_model_name_ = memory_model_name;
}
void ConfigProtocol::set_wl_memory_model(const CircuitModelId& memory_model) {
if (BLWL_PROTOCOL_SHIFT_REGISTER != wl_protocol_type_) {
VTR_LOG_ERROR("WL protocol memory model is only applicable when '%d' is defined", BLWL_PROTOCOL_TYPE_STRING[wl_protocol_type_]);
return;
}
wl_memory_model_ = memory_model;
}

29
libopenfpga/libarchopenfpga/src/config_protocol.h
View File

@ -10,7 +10,7 @@ enum e_blwl_protocol_type {
BLWL_PROTOCOL_FLATTEN,
BLWL_PROTOCOL_DECODER,
BLWL_PROTOCOL_SHIFT_REGISTER,
NUM_BLWL_PROTOCOLS_TYPES
NUM_BLWL_PROTOCOL_TYPES
};
constexpr std::array<const char*, NUM_BLWL_PROTOCOL_TYPES> BLWL_PROTOCOL_TYPE_STRING = {{"flatten", "decoder", "shift_register"}};
@ -25,11 +25,25 @@ class ConfigProtocol {
std::string memory_model_name() const;
CircuitModelId memory_model() const;
int num_regions() const;
e_blwl_protocol_type bl_protocol_type() const;
std::string bl_memory_model_name() const;
CircuitModelId bl_memory_model() const;
e_blwl_protocol_type wl_protocol_type() const;
std::string wl_memory_model_name() const;
CircuitModelId wl_memory_model() const;
public: /* Public Mutators */
void set_type(const e_config_protocol_type& type);
void set_memory_model_name(const std::string& memory_model_name);
void set_memory_model(const CircuitModelId& memory_model);
void set_num_regions(const int& num_regions);
void set_bl_protocol_type(const e_blwl_protocol_type& type);
void set_bl_memory_model_name(const std::string& memory_model_name);
void set_bl_memory_model(const CircuitModelId& memory_model);
void set_wl_protocol_type(const e_blwl_protocol_type& type);
void set_wl_memory_model_name(const std::string& memory_model_name);
void set_wl_memory_model(const CircuitModelId& memory_model);
private: /* Internal data */
/* The type of configuration protocol.
* In other words, it is about how to organize and access each configurable memory
@ -42,6 +56,19 @@ class ConfigProtocol {
/* Number of configurable regions */
int num_regions_;
/* BL & WL protocol: This is only applicable to memory-bank configuration protocols
* - type: defines which protocol to be used. By default, we consider decoders
* - bl/wl_memory_model: defines the circuit model to be used when building shift register chains for BL/WL configuration.
* It must be a valid CCFF circuit model. This is only applicable when shift-register protocol is selected
* for BL or WL.
*/
e_blwl_protocol_type bl_protocol_type_ = BLWL_PROTOCOL_DECODER;
std::string bl_memory_model_name_;
CircuitModelId bl_memory_model_;
e_blwl_protocol_type wl_protocol_type_ = BLWL_PROTOCOL_DECODER;
std::string wl_memory_model_name_;
CircuitModelId wl_memory_model_;
};
#endif

23
libopenfpga/libarchopenfpga/src/openfpga_arch_linker.cpp
View File

@ -22,6 +22,29 @@ void link_config_protocol_to_circuit_library(openfpga::Arch& openfpga_arch) {
}
openfpga_arch.config_protocol.set_memory_model(config_memory_model);
/* Optional: we need to bind the memory model for BL/WL protocols */
if (!openfpga_arch.config_protocol.bl_memory_model_name().empty()) {
CircuitModelId bl_memory_model = openfpga_arch.circuit_lib.model(openfpga_arch.config_protocol.bl_memory_model_name());
/* Error out if the circuit model id is invalid */
if (CircuitModelId::INVALID() == bl_memory_model) {
VTR_LOG("Invalid bl memory model name '%s' defined in <configuration_protocol>!",
openfpga_arch.config_protocol.bl_memory_model_name().c_str());
exit(1);
}
openfpga_arch.config_protocol.set_bl_memory_model(bl_memory_model);
}
if (!openfpga_arch.config_protocol.wl_memory_model_name().empty()) {
CircuitModelId wl_memory_model = openfpga_arch.circuit_lib.model(openfpga_arch.config_protocol.wl_memory_model_name());
/* Error out if the circuit model id is invalid */
if (CircuitModelId::INVALID() == wl_memory_model) {
VTR_LOG("Invalid wl memory model name '%s' defined in <configuration_protocol>!",
openfpga_arch.config_protocol.wl_memory_model_name().c_str());
exit(1);
}
openfpga_arch.config_protocol.set_wl_memory_model(wl_memory_model);
}
}
/********************************************************************

76
libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp
View File

@ -33,6 +33,73 @@ e_config_protocol_type string_to_config_protocol_type(const std::string& type_st
return NUM_CONFIG_PROTOCOL_TYPES;
}
/********************************************************************
* Convert string to the enumerate of BL/WL protocol type
*******************************************************************/
static
e_blwl_protocol_type string_to_blwl_protocol_type(const std::string& type_string) {
for (size_t itype = 0; itype < NUM_BLWL_PROTOCOL_TYPES; ++itype) {
if (std::string(BLWL_PROTOCOL_TYPE_STRING[itype]) == type_string) {
return static_cast<e_blwl_protocol_type>(itype);
}
}
return NUM_BLWL_PROTOCOL_TYPES;
}
/********************************************************************
* Parse XML codes of a <bl> to an object of configuration protocol
*******************************************************************/
static
void read_xml_bl_protocol(pugi::xml_node& xml_bl_protocol,
const pugiutil::loc_data& loc_data,
ConfigProtocol& config_protocol) {
/* Find the type of configuration protocol */
const char* type_attr = get_attribute(xml_bl_protocol, "protocol", loc_data).value();
/* Translate the type of design technology to enumerate */
e_blwl_protocol_type blwl_protocol_type = string_to_blwl_protocol_type(std::string(type_attr));
if (NUM_BLWL_PROTOCOL_TYPES == blwl_protocol_type) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_bl_protocol),
"Invalid 'protocol' attribute '%s'\n",
type_attr);
}
config_protocol.set_bl_protocol_type(blwl_protocol_type);
/* Find the memory model, only applicable to shift-registor protocol */
if (BLWL_PROTOCOL_SHIFT_REGISTER == blwl_protocol_type) {
config_protocol.set_bl_memory_model_name(get_attribute(xml_bl_protocol, "circuit_model_name", loc_data).as_string());
}
}
/********************************************************************
* Parse XML codes of a <wl> to an object of configuration protocol
*******************************************************************/
static
void read_xml_wl_protocol(pugi::xml_node& xml_wl_protocol,
const pugiutil::loc_data& loc_data,
ConfigProtocol& config_protocol) {
/* Find the type of configuration protocol */
const char* type_attr = get_attribute(xml_wl_protocol, "protocol", loc_data).value();
/* Translate the type of design technology to enumerate */
e_blwl_protocol_type blwl_protocol_type = string_to_blwl_protocol_type(std::string(type_attr));
if (NUM_BLWL_PROTOCOL_TYPES == blwl_protocol_type) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_wl_protocol),
"Invalid 'protocol' attribute '%s'\n",
type_attr);
}
config_protocol.set_wl_protocol_type(blwl_protocol_type);
/* Find the memory model, only applicable to shift-registor protocol */
if (BLWL_PROTOCOL_SHIFT_REGISTER == blwl_protocol_type) {
config_protocol.set_wl_memory_model_name(get_attribute(xml_wl_protocol, "circuit_model_name", loc_data).as_string());
}
}
/********************************************************************
* Parse XML codes of a <organization> to an object of configuration protocol
*******************************************************************/
@ -65,6 +132,15 @@ void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
"Invalid 'num_region=%d' definition. At least 1 region should be defined!\n",
config_protocol.num_regions());
}
/* Parse BL & WL protocols */
if (config_protocol.type() == CONFIG_MEM_QL_MEMORY_BANK) {
pugi::xml_node xml_bl_protocol = get_single_child(xml_config_orgz, "bl", loc_data);
read_xml_bl_protocol(xml_bl_protocol, loc_data, config_protocol);
pugi::xml_node xml_wl_protocol = get_single_child(xml_config_orgz, "wl", loc_data);
read_xml_wl_protocol(xml_wl_protocol, loc_data, config_protocol);
}
}
/********************************************************************