reserve child block in bistream manager

libopenfpga/libfpgabitstream/src/bitstream_manager.cpp

@@ -198,6 +198,15 @@ void BitstreamManager::set_block_name(const ConfigBlockId& block_id,
   block_names_[block_id] = block_name;
 }
 
+void BitstreamManager::reserve_child_blocks(const ConfigBlockId& parent_block,
+                                            const size_t& num_children) {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_block_id(parent_block));
+
+  /* Add the child_block to the parent_block */
+  child_block_ids_[parent_block].reserve(num_children);
+}
+
 void BitstreamManager::add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block) {
   /* Ensure the input ids are valid */
   VTR_ASSERT(true == valid_block_id(parent_block));

libopenfpga/libfpgabitstream/src/bitstream_manager.h

@@ -163,6 +163,10 @@ class BitstreamManager {
     void set_block_name(const ConfigBlockId& block_id,
                         const std::string& block_name);
 
+    /* Reserve child blocks for a block to be memory efficient */
+    void reserve_child_blocks(const ConfigBlockId& parent_block,
+                              const size_t& num_children);
+
     /* Set a block as a child block of another */
     void add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block);
 

openfpga/src/fpga_bitstream/build_device_bitstream.cpp

@@ -144,6 +144,10 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
   bitstream_manager.reserve_bits(num_bits_to_reserve);
   VTR_LOGV(verbose, "Reserved %lu configuration bits\n", num_bits_to_reserve);
 
+  /* Reserve child blocks for the top level block */
+  bitstream_manager.reserve_child_blocks(top_block,
+                                         openfpga_ctx.module_graph().configurable_children(top_module).size());
+
   /* Create bitstream from grids */
   VTR_LOGV(verbose, "Building grid bitstream...\n");
   build_grid_bitstream(bitstream_manager, top_block,