[Tool] Comment on the memory efficiency on fabric bitstream address storage

2020-10-30 22:09:48 -06:00 · 2020-10-30 22:09:48 -06:00 · 6b25cf720d
parent 7e940980e1
commit 6b25cf720d
1 changed files with 4 additions and 0 deletions
--- a/openfpga/src/fpga_bitstream/fabric_bitstream.h
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream.h
@ -207,6 +207,10 @@ class FabricBitstream {
     * to the configuration protocol directly 
     *
     * We use a 2-element array, as we may have a BL address and a WL address
+     *
+     * TODO: use nested vector may cause large memory footprint 
+     *       when bitstream size increases
+     *       NEED TO THINK ABOUT A COMPACT MODELING
     */
    vtr::vector<FabricBitId, std::vector<char>> bit_addresses_;
    vtr::vector<FabricBitId, std::vector<char>> bit_wl_addresses_;