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[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes

This commit is contained in:
tangxifan 2021-06-29 15:26:40 -06:00
parent 77dddaeb39
commit 7ac7de789e
13 changed files with 113 additions and 167 deletions
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4
openfpga/src/base/openfpga_verilog.cpp
View File

@ -78,6 +78,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_fast_configuration = cmd.option("fast_configuration");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_no_self_checking = cmd.option("no_self_checking");
CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
CommandOptionId opt_verbose = cmd.option("verbose");
@ -93,6 +94,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_top_testbench(true);
options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
options.set_no_self_checking(cmd_context.option_enable(cmd, opt_no_self_checking));
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
}
@ -184,6 +186,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_no_self_checking = cmd.option("no_self_checking");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -196,6 +199,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_preconfig_top_testbench(true);
options.set_no_self_checking(cmd_context.option_enable(cmd, opt_no_self_checking));
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
}

6
openfpga/src/base/openfpga_verilog_command.cpp
View File

@ -97,6 +97,9 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<Openfpg
CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
/* Add an option '--no_self_checking' */
shell_cmd.add_option("no_self_checking", false, "Do not generate self-checking codes for Verilog testbenches.");
/* add an option '--include_signal_init' */
shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
@ -203,6 +206,9 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
/* Add an option '--no_self_checking' */
shell_cmd.add_option("no_self_checking", false, "Do not generate self-checking codes for Verilog testbenches.");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");

14
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -170,10 +170,6 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager,
/* Create directories */
create_directory(src_dir_path);
/* Output preprocessing flags for HDL simulations */
print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
options);
/* Generate full testbench for verification, including configuration phase and operating phase */
std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
print_verilog_full_testbench(module_manager,
@ -195,7 +191,8 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager,
print_verilog_full_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
options.reference_benchmark_file_path(),
options.no_self_checking());
return status;
}
@ -269,10 +266,6 @@ int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager,
/* Create directories */
create_directory(src_dir_path);
/* Output preprocessing flags for HDL simulations */
print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
options);
/* Generate top-level testbench using random vectors */
std::string random_top_testbench_file_path = src_dir_path + netlist_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
print_verilog_random_top_testbench(netlist_name,
@ -289,7 +282,8 @@ int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager,
print_verilog_preconfigured_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path());
options.reference_benchmark_file_path(),
options.no_self_checking());
return status;
}

67
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -97,7 +97,8 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file) {
const std::string& reference_benchmark_file,
const bool& no_self_checking) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
/* Create the file stream */
@ -110,11 +111,6 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
/* Print preprocessing flags */
print_verilog_comment(fp, std::string("------ Include simulation defines -----"));
print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME));
fp << std::endl;
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
if (true == fabric_netlist_file.empty()) {
@ -126,11 +122,12 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
fp << "\t";
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
print_verilog_endif(fp);
fp << std::endl;
if (!no_self_checking) {
fp << "\t";
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
print_verilog_endif(fp);
fp << std::endl;
}
/* Include top-level testbench only when auto-check flag is enabled */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
@ -148,7 +145,8 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file) {
const std::string& reference_benchmark_file,
const bool& no_self_checking) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
/* Create the file stream */
@ -161,11 +159,6 @@ void print_verilog_preconfigured_testbench_include_netlists(const std::string& s
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
/* Print preprocessing flags */
print_verilog_comment(fp, std::string("------ Include simulation defines -----"));
print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME));
fp << std::endl;
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
if (true == fabric_netlist_file.empty()) {
@ -177,11 +170,12 @@ void print_verilog_preconfigured_testbench_include_netlists(const std::string& s
fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
fp << "\t";
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
print_verilog_endif(fp);
fp << std::endl;
if (!no_self_checking) {
fp << "\t";
print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
print_verilog_endif(fp);
fp << std::endl;
}
/* Include formal verification netlists */
print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX));
@ -222,33 +216,4 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
fp.close();
}
/********************************************************************
* Print a Verilog file containing simulation-related preprocessing flags
*******************************************************************/
void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
const VerilogTestbenchOption& verilog_testbench_opts) {
std::string verilog_fname = src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME);
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
/* Validate the file stream */
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features"));
/* To enable auto-checked simulation */
if ( (true == verilog_testbench_opts.print_preconfig_top_testbench())
|| (true == verilog_testbench_opts.print_top_testbench()) ) {
print_verilog_define_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG), 1);
fp << std::endl;
}
/* Close the file stream */
fp.close();
}
} /* end namespace openfpga */

9
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
View File

@ -24,19 +24,18 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file);
const std::string& reference_benchmark_file,
const bool& no_self_checking);
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file);
const std::string& reference_benchmark_file,
const bool& no_self_checking);
void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
const FabricVerilogOption& fabric_verilog_opts);
void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
const VerilogTestbenchOption& verilog_testbench_opts);
} /* end namespace openfpga */
#endif

3
openfpga/src/fpga_verilog/verilog_constants.h
View File

@ -7,8 +7,6 @@ constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v";
constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns
constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v";
@ -19,7 +17,6 @@ constexpr char* TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_top_tb.v"; /* !!! must be
constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_autocheck_top_tb.v"; /* !!! must be consist with the modelsim_autocheck_testbench_module_postfix */
constexpr char* RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_formal_random_top_tb.v";
constexpr char* DEFINES_VERILOG_FILE_NAME = "fpga_defines.v";
constexpr char* DEFINES_VERILOG_SIMULATION_FILE_NAME = "define_simulation.v";
constexpr char* SUBMODULE_VERILOG_FILE_NAME = "sub_module.v";
constexpr char* LOGIC_BLOCK_VERILOG_FILE_NAME = "logic_blocks.v";
constexpr char* LUTS_VERILOG_FILE_NAME = "luts.v";

60
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -57,12 +57,12 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
const std::vector<std::string>& clock_port_names,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const e_verilog_default_net_type& default_net_type) {
const VerilogTestbenchOption& options) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_default_net_type_declaration(fp,
default_net_type);
options.default_net_type());
/* Print the declaration for the module */
fp << "module " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ";" << std::endl;
@ -84,16 +84,17 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX),
std::string(AUTOCHECKED_SIMULATION_FLAG));
options.no_self_checking());
/* Instantiate an integer to count the number of error
* and determine if the simulation succeed or failed
*/
print_verilog_comment(fp, std::string("----- Error counter -------"));
fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl;
/* Add an empty line as splitter */
fp << std::endl;
if (!options.no_self_checking()) {
print_verilog_comment(fp, std::string("----- Error counter -------"));
fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl;
/* Add an empty line as splitter */
fp << std::endl;
}
}
/********************************************************************
@ -108,9 +109,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
/* Validate the file stream */
valid_file_stream(fp);
/* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
/* Instanciate benchmark */
print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
/* Do NOT use explicit port mapping here:
@ -132,12 +131,6 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
/* Condition ends for the benchmark instanciation */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
/********************************************************************
@ -300,7 +293,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
/* Start of testbench */
print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options.default_net_type());
print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options);
/* Call defined top-level module */
print_verilog_random_testbench_fpga_instance(fp, circuit_name,
@ -308,9 +301,11 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
options.explicit_port_mapping());
/* Call defined benchmark */
print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name,
atom_ctx, netlist_annotation,
options.explicit_port_mapping());
if (!options.no_self_checking()) {
print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name,
atom_ctx, netlist_annotation,
options.explicit_port_mapping());
}
/* Find clock port to be used */
std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME));
@ -341,17 +336,18 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
std::string(CHECKFLAG_PORT_POSTFIX),
clock_ports);
print_verilog_testbench_check(fp,
std::string(AUTOCHECKED_SIMULATION_FLAG),
std::string(FORMAL_TB_SIM_START_PORT_NAME),
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX),
std::string(ERROR_COUNTER),
atom_ctx,
netlist_annotation,
clock_port_names,
std::string(DEFAULT_CLOCK_NAME));
if (!options.no_self_checking()) {
print_verilog_testbench_check(fp,
std::string(FORMAL_TB_SIM_START_PORT_NAME),
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX),
std::string(ERROR_COUNTER),
atom_ctx,
netlist_annotation,
clock_port_names,
std::string(DEFAULT_CLOCK_NAME));
}
float simulation_time = find_operating_phase_simulation_time(simulation_parameters.num_clock_cycles(),
1./simulation_parameters.default_operating_clock_frequency(),

2
openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp
View File

@ -93,7 +93,7 @@ void print_verilog_simulation_info(const std::string& ini_fname,
ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period);
ini["SIMULATION_DECK"]["UNIT "] = unit_to_string(options.time_unit());
ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME);
ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME);
ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX));
ini["SIMULATION_DECK"]["CONFIG_PROTOCOL"] = std::string(CONFIG_PROTOCOL_TYPE_STRING[config_protocol_type]);

8
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
View File

@ -75,6 +75,10 @@ bool VerilogTestbenchOption::include_signal_init() const {
return include_signal_init_;
}
bool VerilogTestbenchOption::no_self_checking() const {
return no_self_checking_;
}
e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const {
return default_net_type_;
}
@ -147,6 +151,10 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) {
include_signal_init_ = enabled;
}
void VerilogTestbenchOption::set_no_self_checking(const bool& enabled) {
no_self_checking_ = enabled;
}
void VerilogTestbenchOption::set_default_net_type(const std::string& default_net_type) {
/* Decode from net type string */;
if (default_net_type == std::string(VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE])) {

3
openfpga/src/fpga_verilog/verilog_testbench_options.h
View File

@ -43,6 +43,7 @@ class VerilogTestbenchOption {
std::string simulation_ini_path() const;
bool explicit_port_mapping() const;
bool include_signal_init() const;
bool no_self_checking() const;
e_verilog_default_net_type default_net_type() const;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const;
float time_unit() const;
@ -69,6 +70,7 @@ class VerilogTestbenchOption {
void set_print_simulation_ini(const std::string& simulation_ini_path);
void set_explicit_port_mapping(const bool& enabled);
void set_include_signal_init(const bool& enabled);
void set_no_self_checking(const bool& enabled);
void set_default_net_type(const std::string& default_net_type);
void set_time_unit(const float& time_unit);
void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type);
@ -85,6 +87,7 @@ class VerilogTestbenchOption {
std::string simulation_ini_path_;
bool explicit_port_mapping_;
bool include_signal_init_;
bool no_self_checking_;
e_verilog_default_net_type default_net_type_;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
float time_unit_;

24
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -366,7 +366,6 @@ std::vector<BasicPort> generate_verilog_testbench_clock_port(const std::vector<s
* Restriction: this function only supports single clock benchmarks!
*******************************************************************/
void print_verilog_testbench_check(std::fstream& fp,
const std::string& autochecked_preprocessing_flag,
const std::string& simulation_start_counter_name,
const std::string& benchmark_port_postfix,
const std::string& fpga_port_postfix,
@ -380,9 +379,7 @@ void print_verilog_testbench_check(std::fstream& fp,
/* Validate the file stream */
valid_file_stream(fp);
/* Add output autocheck conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag);
/* Add output autocheck */
print_verilog_comment(fp, std::string("----- Begin checking output vectors -------"));
std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(clock_port_names, default_clock_name);
@ -460,9 +457,6 @@ void print_verilog_testbench_check(std::fstream& fp,
fp << std::endl;
}
/* Condition ends */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
@ -664,7 +658,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
const std::string& benchmark_output_port_postfix,
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix,
const std::string& autocheck_preprocessing_flag) {
const bool& no_self_checking) {
/* Validate the file stream */
valid_file_stream(fp);
@ -718,11 +712,9 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
/* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, std::string(autocheck_preprocessing_flag));
/* Add an empty line as splitter */
fp << std::endl;
if (no_self_checking) {
return;
}
/* Instantiate wire for benchmark output */
print_verilog_comment(fp, std::string("----- Benchmark outputs -------"));
@ -767,12 +759,6 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
/* Condition ends for the benchmark instanciation */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
/********************************************************************

3
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -62,7 +62,6 @@ std::vector<BasicPort> generate_verilog_testbench_clock_port(const std::vector<s
const std::string& default_clock_name);
void print_verilog_testbench_check(std::fstream& fp,
const std::string& autochecked_preprocessing_flag,
const std::string& simulation_start_counter_name,
const std::string& benchmark_port_postfix,
const std::string& fpga_port_postfix,
@ -95,7 +94,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
const std::string& benchmark_output_port_postfix,
const std::string& fpga_output_port_postfix,
const std::string& check_flag_port_postfix,
const std::string& autocheck_preprocessing_flag);
const bool& no_self_checking);
void print_verilog_testbench_signal_initialization(std::fstream& fp,
const std::string& top_instance_name,

77
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -702,12 +702,12 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
const SimulationSetting& simulation_parameters,
const ConfigProtocol& config_protocol,
const std::string& circuit_name,
const e_verilog_default_net_type& default_net_type) {
const VerilogTestbenchOption& options) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_default_net_type_declaration(fp,
default_net_type);
options.default_net_type());
/* Print module definition */
fp << "module " << circuit_name << std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX);
@ -808,13 +808,15 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::string(AUTOCHECKED_SIMULATION_FLAG));
options.no_self_checking());
/* Instantiate an integer to count the number of error and
* determine if the simulation succeed or failed
*/
print_verilog_comment(fp, std::string("----- Error counter: Deposit an error for config_done signal is not raised at the beginning -----"));
fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 1;" << std::endl;
if (!options.no_self_checking()) {
print_verilog_comment(fp, std::string("----- Error counter: Deposit an error for config_done signal is not raised at the beginning -----"));
fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 1;" << std::endl;
}
}
/********************************************************************
@ -914,9 +916,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
/* Validate the file stream */
valid_file_stream(fp);
/* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
/* Instanciate benchmark */
print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
/* Do NOT use explicit port mapping here:
@ -938,12 +938,6 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
/* Add an empty line as splitter */
fp << std::endl;
/* Condition ends for the benchmark instanciation */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
/********************************************************************
@ -1811,16 +1805,12 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp,
*******************************************************************/
static
void print_verilog_top_testbench_check(std::fstream& fp,
const std::string& autochecked_preprocessing_flag,
const std::string& config_done_port_name,
const std::string& error_counter_name) {
/* Validate the file stream */
valid_file_stream(fp);
/* Add output autocheck conditionally: only when a preprocessing flag is enable */
print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag);
print_verilog_comment(fp, std::string("----- Configuration done must be raised in the end -------"));
BasicPort config_done_port(config_done_port_name, 1);
@ -1834,9 +1824,6 @@ void print_verilog_top_testbench_check(std::fstream& fp,
write_tab_to_file(fp, 1);
fp << "end" << std::endl;
/* Condition ends */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
}
@ -1925,7 +1912,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
pin_constraints,
simulation_parameters, config_protocol,
circuit_name,
options.default_net_type());
options);
/* Find the clock period */
float prog_clock_period = (1./simulation_parameters.programming_clock_frequency());
@ -2006,11 +1993,13 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
/* Instanciate input benchmark */
print_verilog_top_testbench_benchmark_instance(fp,
circuit_name,
atom_ctx,
netlist_annotation,
explicit_port_mapping);
if (!options.no_self_checking()) {
print_verilog_top_testbench_benchmark_instance(fp,
circuit_name,
atom_ctx,
netlist_annotation,
explicit_port_mapping);
}
/* load bitstream to FPGA fabric in a configuration phase */
print_verilog_full_testbench_bitstream(fp,
@ -2051,24 +2040,24 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::vector<BasicPort>(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1)));
/* Add output autocheck */
print_verilog_testbench_check(fp,
std::string(AUTOCHECKED_SIMULATION_FLAG),
std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::string(TOP_TESTBENCH_ERROR_COUNTER),
atom_ctx,
netlist_annotation,
clock_port_names,
std::string(TOP_TB_OP_CLOCK_PORT_NAME));
if (!options.no_self_checking()) {
/* Add output autocheck */
print_verilog_testbench_check(fp,
std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::string(TOP_TESTBENCH_ERROR_COUNTER),
atom_ctx,
netlist_annotation,
clock_port_names,
std::string(TOP_TB_OP_CLOCK_PORT_NAME));
/* Add autocheck for configuration phase */
print_verilog_top_testbench_check(fp,
std::string(AUTOCHECKED_SIMULATION_FLAG),
std::string(TOP_TB_CONFIG_DONE_PORT_NAME),
std::string(TOP_TESTBENCH_ERROR_COUNTER));
/* Add autocheck for configuration phase */
print_verilog_top_testbench_check(fp,
std::string(TOP_TB_CONFIG_DONE_PORT_NAME),
std::string(TOP_TESTBENCH_ERROR_COUNTER));
}
/* Find simulation time */
float simulation_time = find_simulation_time_period(VERILOG_SIM_TIMESCALE,