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[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time

This commit is contained in:
tangxifan 2021-06-29 09:56:04 -06:00
parent 74148ec491
commit dfe1db996a
4 changed files with 5 additions and 10 deletions
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4
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -41,7 +41,6 @@ constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT";
constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT";
constexpr char* ERROR_COUNTER = "nb_error";
constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start";
constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200;
/********************************************************************
* Print the module ports for the Verilog testbench
@ -354,8 +353,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
clock_port_names,
std::string(DEFAULT_CLOCK_NAME));
float simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME,
simulation_parameters.num_clock_cycles(),
float simulation_time = find_operating_phase_simulation_time(simulation_parameters.num_clock_cycles(),
1./simulation_parameters.default_operating_clock_frequency(),
VERILOG_SIM_TIMESCALE);

3
openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp
View File

@ -72,8 +72,7 @@ void print_verilog_simulation_info(const std::string& ini_fname,
1. / op_clock_freq);
} else {
VTR_ASSERT(options.print_preconfig_top_testbench());
simulation_time_period = find_operating_phase_simulation_time(1.,
num_operating_clock_cycles,
simulation_time_period = find_operating_phase_simulation_time(num_operating_clock_cycles,
1. / op_clock_freq,
options.time_unit());
}

5
openfpga/src/utils/simulation_utils.cpp
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@ -14,14 +14,13 @@ namespace openfpga {
/********************************************************************
* Compute the time period for the simulation
*******************************************************************/
float find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
float find_operating_phase_simulation_time(const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale) {
/* Take into account the prog_reset and reset cycles
* 1e9 is to change the unit to ns rather than second
*/
return ((float)factor * (float)num_op_clock_cycles * op_clock_period) / timescale;
return ((float)num_op_clock_cycles * op_clock_period) / timescale;
}
/********************************************************************

3
openfpga/src/utils/simulation_utils.h
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@ -12,8 +12,7 @@
/* begin namespace openfpga */
namespace openfpga {
float find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
float find_operating_phase_simulation_time(const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale);