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[Tool] Relex logic block checking codes to skip zero-capacity nodes

This commit is contained in:
tangxifan 2020-11-02 16:57:19 -07:00
parent 3b49e6d090
commit 1fd899ecee
2 changed files with 16 additions and 11 deletions
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22
openfpga/src/repack/check_lb_rr_graph.cpp
View File

@ -76,6 +76,10 @@ static bool check_lb_rr_graph_dangling_nodes(const LbRRGraph& lb_rr_graph) {
* If so, this is a dangling nodes and report
*/
for (auto node : lb_rr_graph.nodes()) {
/* Bypass 0-capacity node; They can be dangling */
if (0 == lb_rr_graph.node_capacity(node)) {
continue;
}
if ((0 == lb_rr_graph.node_in_edges(node).size())
&& (0 == lb_rr_graph.node_out_edges(node).size())) {
/* Print a warning! */
@ -105,6 +109,10 @@ static bool check_lb_rr_graph_source_nodes(const LbRRGraph& lb_rr_graph) {
if (LB_SOURCE != lb_rr_graph.node_type(node)) {
continue;
}
/* Bypass 0-capacity node; They can be dangling */
if (0 == lb_rr_graph.node_capacity(node)) {
continue;
}
if ((0 != lb_rr_graph.node_in_edges(node).size())
|| (0 == lb_rr_graph.node_out_edges(node).size())) {
/* Print a warning! */
@ -134,6 +142,10 @@ static bool check_lb_rr_graph_sink_nodes(const LbRRGraph& lb_rr_graph) {
if (LB_SINK != lb_rr_graph.node_type(node)) {
continue;
}
/* Bypass 0-capacity node; They can be dangling */
if (0 == lb_rr_graph.node_capacity(node)) {
continue;
}
if ((0 == lb_rr_graph.node_in_edges(node).size())
|| (0 != lb_rr_graph.node_out_edges(node).size())) {
/* Print a warning! */
@ -184,16 +196,6 @@ bool check_lb_rr_graph(const LbRRGraph& lb_rr_graph) {
num_err++;
}
if (false == check_lb_rr_graph_source_nodes(lb_rr_graph)) {
VTR_LOG_WARN("Fail in checking source nodes!\n");
num_err++;
}
if (false == check_lb_rr_graph_sink_nodes(lb_rr_graph)) {
VTR_LOG_WARN("Fail in checking sink nodes!\n");
num_err++;
}
/* Error out if there is any fatal errors found */
if (0 < num_err) {
VTR_LOG_WARN("Checked Logical tile Routing Resource graph with %d errors !\n",

5
openfpga/src/repack/lb_rr_graph_utils.cpp
View File

@ -63,7 +63,10 @@ void print_lb_rr_node(const LbRRGraph& lb_rr_graph,
VTR_LOG("Node id: %d\n", size_t(node));
VTR_LOG("Node type: %s\n", lb_rr_type_str[lb_rr_graph.node_type(node)]);
VTR_LOG("Node capacity: %d\n", lb_rr_graph.node_capacity(node));
VTR_LOG("Node pb_graph_pin: %s\n", lb_rr_graph.node_pb_graph_pin(node)->to_string().c_str());
/* Some node, e.g., SOURCE, SINK may not have pb_graph_pin, skip outputing in this case */
if (nullptr != lb_rr_graph.node_pb_graph_pin(node)) {
VTR_LOG("Node pb_graph_pin: %s\n", lb_rr_graph.node_pb_graph_pin(node)->to_string().c_str());
}
VTR_LOG("Node intrinsic_cost: %f\n", lb_rr_graph.node_intrinsic_cost(node));
VTR_LOG("Node num in_edges: %ld\n", lb_rr_graph.node_in_edges(node).size());
VTR_LOG("Node num out_edges: %ld\n", lb_rr_graph.node_out_edges(node).size());