riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

move constants from verilog domain to common so that FPGA-SPICE can share

This commit is contained in:
tangxifan 2020-07-05 11:39:46 -06:00
parent 7c2a0a6ad2
commit 1ad6e8292a
3 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h
View File

@ -52,6 +52,10 @@ constexpr char* INV_PORT_POSTFIX = "_inv";
/* Bitstream file strings */
constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";
constexpr char* DEFAULT_LB_DIR_NAME = "lb/";
constexpr char* DEFAULT_RR_DIR_NAME = "routing/";
constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
} /* end namespace openfpga */
#endif

1
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -11,6 +11,7 @@
/* Headers from openfpgautil library */
#include "openfpga_digest.h"
#include "openfpga_reserved_words.h"
#include "device_rr_gsb.h"
#include "verilog_constants.h"

3
openfpga/src/fpga_verilog/verilog_constants.h
View File

@ -13,9 +13,6 @@ constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to e
constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification
constexpr char* DEFAULT_LB_DIR_NAME = "lb/";
constexpr char* DEFAULT_RR_DIR_NAME = "routing/";
constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
// Icarus variables and flag