diff --git a/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h b/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h
index e6b89a10b..3f27c6966 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h
+++ b/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h
@@ -52,6 +52,10 @@ constexpr char* INV_PORT_POSTFIX = "_inv";
 /* Bitstream file strings */
 constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";
 
+constexpr char* DEFAULT_LB_DIR_NAME = "lb/";
+constexpr char* DEFAULT_RR_DIR_NAME = "routing/";
+constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 0e2f84124..7f4c0d9b7 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -11,6 +11,7 @@
 
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
+#include "openfpga_reserved_words.h"
 
 #include "device_rr_gsb.h"
 #include "verilog_constants.h"
diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index 3266fe2f6..a09425d4f 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -13,9 +13,6 @@ constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to e
 constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
 constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification
 
-constexpr char* DEFAULT_LB_DIR_NAME = "lb/";
-constexpr char* DEFAULT_RR_DIR_NAME = "routing/";
-constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
 constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
 
 // Icarus variables and flag