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[Engine] Update BL/WL estimation function for QL memory bank protocol

This commit is contained in:
tangxifan 2021-09-05 11:53:33 -07:00
parent 5759f5f35b
commit f75456e304
1 changed files with 4 additions and 4 deletions
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8
openfpga/src/fabric/build_top_module_memory.cpp
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@ -689,8 +689,8 @@ vtr::vector<ConfigRegionId, TopModuleNumConfigBits> find_top_module_regional_num
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id];
num_bls[coord.x()] = std::max(num_bls[coord.x()], find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type));
num_wls[coord.y()] = std::max(num_wls[coord.y()], find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type));
num_bls[coord.x()] = std::max(num_bls[coord.x()], find_memory_decoder_addr_size(find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type)));
num_wls[coord.y()] = std::max(num_wls[coord.y()], find_memory_decoder_addr_size(find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type)));
for (const auto& kv : num_bls) {
num_config_bits[config_region].first += kv.first;
}
@ -850,7 +850,7 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
/* BL address size is the largest among all the regions */
size_t bl_addr_size = 0;
for (const ConfigRegionId& config_region : module_manager.regions(module_id)) {
bl_addr_size = std::max(bl_addr_size, find_memory_decoder_addr_size(num_config_bits[config_region].first));
bl_addr_size = std::max(bl_addr_size, num_config_bits[config_region].first);
}
BasicPort bl_addr_port(std::string(DECODER_BL_ADDRESS_PORT_NAME), bl_addr_size);
module_manager.add_port(module_id, bl_addr_port, ModuleManager::MODULE_INPUT_PORT);
@ -858,7 +858,7 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
/* WL address size is the largest among all the regions */
size_t wl_addr_size = 0;
for (const ConfigRegionId& config_region : module_manager.regions(module_id)) {
wl_addr_size = std::max(wl_addr_size, find_memory_decoder_addr_size(num_config_bits[config_region].second));
wl_addr_size = std::max(wl_addr_size, num_config_bits[config_region].second);
}
BasicPort wl_addr_port(std::string(DECODER_WL_ADDRESS_PORT_NAME), wl_addr_size);
module_manager.add_port(module_id, wl_addr_port, ModuleManager::MODULE_INPUT_PORT);