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[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose

This commit is contained in:
tangxifan 2021-06-29 15:42:23 -06:00
parent ac9046b7d2
commit 6a260cadbf
4 changed files with 3 additions and 16 deletions
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4
openfpga/src/base/openfpga_verilog.cpp
View File

@ -78,7 +78,6 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_fast_configuration = cmd.option("fast_configuration");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_no_self_checking = cmd.option("no_self_checking");
CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
CommandOptionId opt_verbose = cmd.option("verbose");
@ -94,7 +93,6 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_top_testbench(true);
options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
options.set_no_self_checking(cmd_context.option_enable(cmd, opt_no_self_checking));
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
}
@ -186,7 +184,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_no_self_checking = cmd.option("no_self_checking");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -199,7 +196,6 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_preconfig_top_testbench(true);
options.set_no_self_checking(cmd_context.option_enable(cmd, opt_no_self_checking));
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
}

7
openfpga/src/base/openfpga_verilog_command.cpp
View File

@ -196,7 +196,7 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING);
/* Add an option '--reference_benchmark_file_path'*/
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "Specify the file path to the reference Verilog netlist. If specified, the testbench will include self-checking codes");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
/* Add an option '--explicit_port_mapping' */
@ -206,9 +206,6 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
/* Add an option '--no_self_checking' */
shell_cmd.add_option("no_self_checking", false, "Do not generate self-checking codes for Verilog testbenches.");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");
@ -244,7 +241,7 @@ ShellCommandId add_openfpga_write_simulation_task_info_command(openfpga::Shell<O
shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING);
/* Add an option '--reference_benchmark_file_path'*/
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "Specify the file path to the reference Verilog netlist. If specified, the testbench will include self-checking codes");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
/* Add an option '--testbench_type'*/

6
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
View File

@ -76,7 +76,7 @@ bool VerilogTestbenchOption::include_signal_init() const {
}
bool VerilogTestbenchOption::no_self_checking() const {
return no_self_checking_;
return reference_benchmark_file_path_.empty();
}
e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const {
@ -151,10 +151,6 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) {
include_signal_init_ = enabled;
}
void VerilogTestbenchOption::set_no_self_checking(const bool& enabled) {
no_self_checking_ = enabled;
}
void VerilogTestbenchOption::set_default_net_type(const std::string& default_net_type) {
/* Decode from net type string */;
if (default_net_type == std::string(VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE])) {

2
openfpga/src/fpga_verilog/verilog_testbench_options.h
View File

@ -70,7 +70,6 @@ class VerilogTestbenchOption {
void set_print_simulation_ini(const std::string& simulation_ini_path);
void set_explicit_port_mapping(const bool& enabled);
void set_include_signal_init(const bool& enabled);
void set_no_self_checking(const bool& enabled);
void set_default_net_type(const std::string& default_net_type);
void set_time_unit(const float& time_unit);
void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type);
@ -87,7 +86,6 @@ class VerilogTestbenchOption {
std::string simulation_ini_path_;
bool explicit_port_mapping_;
bool include_signal_init_;
bool no_self_checking_;
e_verilog_default_net_type default_net_type_;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
float time_unit_;