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[Doc] Remove ``define_simulation.v`` since it is no longer needed.

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tangxifan 2021-06-29 15:38:35 -06:00
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19
docs/source/manual/fpga_verilog/testbench.rst
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@ -58,8 +58,8 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. _fig_verilog_testbench_hierarchy:
.. figure:: ./figures/verilog_testbench_hierarchy.png
:scale: 90%
.. figure:: ./figures/verilog_testbench_hierarchy.svg
:scale: 100%
Hierarchy of Verilog testbenches for a FPGA fabric implemented with an application
@ -73,21 +73,6 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. note:: Fabric Verilog netlists are included in this file.
.. option:: define_simulation.v
This file includes pre-processing flags required by the testbenches, to smooth HDL simulation.
It will include the folliwng pre-procesing flags:
- ```define AUTOCHECK_SIMULATION`` When enabled, testbench will include self-testing features. The FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag.
.. note:: OpenFPGA always enable the self-testing feature. Users can disable it by commenting out the associated line in the ``define_simulation.v``.
- ```define ENABLE_FORMAL_VERFICATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the pre-configured FPGA netlist for formal verification usage. This flag is added when ``--print_formal_verification_top_netlist`` option is enabled when calling the ``write_verilog_testbench`` command.
- ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command.
.. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled!
.. option:: <bench_name>_autocheck_top_tb.v
This is the netlist for full testbench.

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docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
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@ -51,7 +51,9 @@ write_full_testbench
.. option:: --reference_benchmark_file_path <string>
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. note:: If not specified, the testbench will not include any self-checking feature!
.. option:: --pin_constraints_file <string> or -pcf <string>
@ -150,7 +152,9 @@ write_preconfigured_testbench
.. option:: --reference_benchmark_file_path <string>
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. note:: If not specified, the testbench will not include any self-checking feature!
.. option:: --pin_constraints_file <string> or -pcf <string>