From ac9046b7d20c560c9a8b9ab5e47f06f7e360497e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 15:38:35 -0600 Subject: [PATCH] [Doc] Remove ``define_simulation.v`` since it is no longer needed. --- .../figures/verilog_testbench_hierarchy.png | Bin 32203 -> 0 bytes .../figures/verilog_testbench_hierarchy.svg | 79 ++++++++++++++++++ docs/source/manual/fpga_verilog/testbench.rst | 19 +---- .../fpga_verilog_commands.rst | 8 +- 4 files changed, 87 insertions(+), 19 deletions(-) delete mode 100644 docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.png create mode 100644 docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.svg diff --git a/docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.png b/docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.png deleted file mode 100644 index 042fb8eaf9212cf82e1f391990108b6b23cb045f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 32203 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The FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag. - - .. note:: OpenFPGA always enable the self-testing feature. Users can disable it by commenting out the associated line in the ``define_simulation.v``. - - - ```define ENABLE_FORMAL_VERFICATION`` When enabled, the ``_include_netlist.v`` will include the pre-configured FPGA netlist for formal verification usage. This flag is added when ``--print_formal_verification_top_netlist`` option is enabled when calling the ``write_verilog_testbench`` command. - - - ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command. - - .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled! - .. option:: _autocheck_top_tb.v This is the netlist for full testbench. diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index d8e254a3e..e927d7b2c 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -51,7 +51,9 @@ write_full_testbench .. option:: --reference_benchmark_file_path - Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + + .. note:: If not specified, the testbench will not include any self-checking feature! .. option:: --pin_constraints_file or -pcf @@ -150,7 +152,9 @@ write_preconfigured_testbench .. option:: --reference_benchmark_file_path - Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + + .. note:: If not specified, the testbench will not include any self-checking feature! .. option:: --pin_constraints_file or -pcf