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824 Commits

Author SHA1 Message Date
David Shah fae3e645a2 ecp5: Add 'fake' DCU parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-09 18:25:42 +00:00
David Shah 960c8794fa ecp5: Add blackboxes for ancillary DCU cells 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-09 15:18:30 +00:00
David Shah 1f51332808 ecp5: Adding some blackbox cells 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-07 14:56:38 +00:00
Clifford Wolf d084fb4c3f Fix sf2 LUT interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-31 15:36:53 +01:00
Clifford Wolf cf79fd4376 Basic SmartFusion2 and IGLOO2 synthesis support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-31 15:28:57 +01:00
David Shah b65932edc4 ecp5: Remove DSP parameters that don't work 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-22 16:20:38 +01:00
David Shah 101f5234ff ecp5: Add DSP blackboxes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-21 19:27:02 +01:00
David Shah d29b517fef ecp5: Sim model fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 15:16:40 +01:00
David Shah 677b8ed3ca ecp5: Add latch inference 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 15:16:40 +01:00
Clifford Wolf 24a5c65856
Merge pull request #657 from mithro/xilinx-vpr 
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
 2018-10-18 10:54:03 +02:00
David Shah df4bfa0ad6 ecp5: Disable LSR inversion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-16 12:48:39 +01:00
David Shah 812538a036 BRAM improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-12 14:22:21 +01:00
David Shah bdfead8c64 ecp5: Adding BRAM maps for all size options 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 17:18:17 +01:00
David Shah 983fb7ff88 ecp5: First BRAM type maps successfully 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:35:19 +01:00
David Shah 2ef1af8b58 ecp5: Script for BRAM IO connections 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:11:00 +01:00
David Shah 346cbbdbdc ecp5: Adding BRAM initialisation and config 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-09 14:19:04 +01:00
Tim 'mithro' Ansell b111ea1228 xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. 
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
 2018-10-08 16:52:12 -07:00
David Shah 31e22c8b96 ecp5: Add blackbox for DP16KD 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 11:35:59 +01:00
Clifford Wolf 5f1fea08d5 Add inout ports to cells_xtra.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-04 11:30:55 +02:00
Tim Ansell ad975fb694
xilinx: Adding missing inout IO port to IOBUF 2018-10-03 16:38:32 -07:00
Clifford Wolf 76baae4b94
Merge pull request #645 from daveshah1/ecp5_dram_fix 
ecp5: Don't map ROMs to DRAM
 2018-10-02 10:00:10 +02:00
David Shah fcd39e1398 ecp5: Don't map ROMs to DRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 18:34:41 +01:00
Clifford Wolf 51f1bbeeb0 Add iCE40 SB_SPRAM256KA simulation model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-10 11:57:24 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
David Shah 3a3558acce ecp5: Fixing miscellaneous sim model issues 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 15:56:12 +02:00
David Shah e9ef077266 ecp5: Fixing 'X' issues with LUT simulation models 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 15:20:34 +02:00
David Shah b2c62ff8ef ecp5: ECP5 synthesis fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 14:33:13 +02:00
David Shah 459d367913 ecp5: Adding synchronous set/reset support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-14 16:18:01 +02:00
David Shah 241429abac ecp5: Add DRAM match rule 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 16:25:52 +02:00
David Shah 4a60bc83ab ecp5: Cells and mappings fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 16:14:08 +02:00
David Shah b0fea67cc6 ecp5: Fixing arith_map 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 15:49:59 +02:00
David Shah 11c916840d ecp5: Initial arith_map implementation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 15:46:12 +02:00
David Shah c2d7be140a ecp5: Adding basic synth_ecp5 based on synth_ice40 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:52:25 +02:00
David Shah eb8f3f7dc4 ecp5: Adding DFF maps 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:32:23 +02:00
David Shah 1def34f2a6 ecp5: Adding DRAM map 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:08:42 +02:00
David Shah b1b9e23f94 ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 13:27:24 +02:00
David Shah cd65eeb3b3 ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 13:09:18 +02:00
Clifford Wolf 57fc8dd582 Add "synth_ice40 -json" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-13 13:35:10 +02:00
Clifford Wolf 83631555dd Fix ice40_opt for cases where a port is connected to a signal with width != 1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-11 18:12:42 +02:00
Clifford Wolf 7fecc3c199 Make -nordff the default in "prep" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-30 13:17:09 +02:00
Olof Kindgren faac2c5595 Avoid mixing module port declaration styles in ice40 cells_sim.v 
The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
 2018-05-17 13:54:43 +02:00
Clifford Wolf 47eb150eec
Merge pull request #537 from mithro/yosys-vpr 
Improving Yosys when used with VPR
 2018-05-04 12:32:30 +02:00
Clifford Wolf b4c1d3084f Add "synth_intel --noiopads" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-30 13:02:56 +02:00
Tim 'mithro' Ansell d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
 2018-04-18 16:55:12 -07:00
Tim 'mithro' Ansell ca39e493ba synth_ice40: Rework the vpr blif output slightly. 2018-04-18 16:55:08 -07:00
Clifford Wolf 81a457c4a6 Add "synth_ice40 -nodffe" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-16 20:44:26 +02:00
c60k28 efed2420d6 Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device 2018-03-31 22:48:47 -06:00
Robert Ou 14e49fb057 coolrunner2: Add an ANDTERM/XOR between chained FFs 
In some cases (e.g. the low bits of counters) the design might end up
with a flip-flop whose input is directly driven by another flip-flop.
This isn't possible in the Coolrunner-II architecture, so add a single
AND term and XOR in this case.
 2018-03-31 03:54:48 -07:00
Robert Ou cfa3753b89 coolrunner2: Split multi-bit nets 
The PAR tool doesn't expect any "dangling" nets with no drivers nor
sinks. By splitting the nets, clean removes them.
 2018-03-31 02:56:11 -07:00
Robert Ou 8fe9cdf364 coolrunner2: Add extraction for TFFs 2018-03-31 02:54:26 -07:00
Larry Doolittle efaef82f75 Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
Clifford Wolf 6991c132b5 Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00
Clifford Wolf 27dd500d31 Add "synth -noshare" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 17:13:45 +01:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Robert Ou 2abcd98527 coolrunner2: Move LOC attributes onto the IO cells 2018-01-17 16:17:32 -08:00
Clifford Wolf 9ac560f5d3 Add "dffinit -highlow" and fix synth_intel 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-09 18:42:19 +01:00
Clifford Wolf b66d50e62d Fix minor typo in "prep" help message 2017-12-19 21:44:05 +01:00
Graham Edgecombe f93e6637aa Fix port names in SB_IO_OD 2017-12-10 15:33:38 +00:00
Graham Edgecombe 52ace35a73 Remove trailing comma from SB_IO_OD port list 
This isn't compatible with Icarus Verilog.
 2017-12-10 15:33:38 +00:00
Tim Ansell 3cc31f197c
Fix spelling in -vpr help for synth_ice40 2017-12-08 18:44:45 -08:00
Clifford Wolf 1f6e8f86c5
Merge pull request #462 from daveshah1/up5k 
Add remaining UltraPlus cells to ice40 techlib
 2017-11-28 15:53:53 +01:00
David Shah 5e8d1922a4 Add remaining UltraPlus cells to ice40 techlib 2017-11-28 11:07:49 +00:00
Clifford Wolf 4782d59a3f
Merge pull request #455 from daveshah1/up5k 
Add UltraPlus specific cells to ice40 techlib
 2017-11-18 19:12:48 +01:00
David Shah 0505f1043c Remove unnecessary keep attributes 2017-11-18 17:53:21 +00:00
Clifford Wolf c01df04e32
Merge pull request #453 from dh73/master 
Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
 2017-11-18 09:56:36 +01:00
David Shah 8ae73e60e2 Merge branch 'master' into up5k 2017-11-17 15:15:39 +00:00
Clifford Wolf 234726c655 Add "synth_ice40 -vpr" 2017-11-16 21:37:02 +01:00
David Shah f9f3ca5da0 Add some UltraPlus cells to ice40 techlib 2017-11-16 12:24:35 +00:00
dh73 3fd1d61e2a Initial Cyclone 10 support 2017-11-08 22:45:21 -06:00
dh73 1fc061d90c Organizing Speedster file names 2017-11-08 20:23:55 -06:00
Larry Doolittle 50bcd9a728 Clean whitespace and permissions in techlibs/intel 2017-10-05 16:23:49 +02:00
Clifford Wolf 65f91e5120 Rename "write_verilog -nobasenradix" to "write_verilog -decimal" 2017-10-03 17:31:21 +02:00
dh73 4718e65763 Tested and working altsyncarm without init files 2017-10-01 19:59:45 -05:00
dh73 cbaba62401 Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now 2017-10-01 11:04:17 -05:00
Clifford Wolf c5b204d8d2 Add first draft of eASIC back-end 2017-09-29 17:53:43 +02:00
Clifford Wolf e64b9d5a4d Fix synth_ice40 doc regarding -top default 2017-09-29 17:52:57 +02:00
Andrew Zonenberg 122532b7e1 Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. 2017-09-14 10:26:32 -07:00
Andrew Zonenberg a84172b23b Initial support for extraction of counters with clock enable 2017-09-14 10:26:10 -07:00
Clifford Wolf 2f75240e36 Merge pull request #406 from azonenberg/coolrunner-techmap 
Coolrunner techmapping improvements
 2017-09-02 13:43:51 +02:00
Robert Ou 5f65e24ccb coolrunner2: Finish fixing special-use p-terms 2017-09-01 07:22:16 -07:00
Robert Ou fa04366f38 coolrunner2: Generate a feed-through AND term when necessary 2017-09-01 07:22:01 -07:00
Robert Ou 6775177171 coolrunner2: Initial fixes for special p-terms 
Certain signals can only be controlled by a product term and not a
sum-of-products. Do the initial work for fixing this.
 2017-09-01 07:21:51 -07:00
Robert Ou 7f08be4304 coolrunner2: Fix mapping of flip-flops 2017-09-01 07:21:39 -07:00
Robert Ou ac84f47829 coolrunner2: Combine some for loops together 2017-09-01 07:21:31 -07:00
Andrew Zonenberg 40021d2fd8 Fixed typo in error message 2017-09-01 06:45:10 -07:00
Andrew Zonenberg fc0c7f74dc Added blackbox $__COUNT_ cell model 2017-09-01 06:44:28 -07:00
Andrew Zonenberg 80aaf50302 Refactoring: moved modules still in cells_sim to cells_sim_wip 2017-09-01 06:44:15 -07:00
Andrew Zonenberg 06754108fc Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction 2017-08-30 16:40:41 -07:00
Andrew Zonenberg 634f18be96 extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos 2017-08-30 16:28:25 -07:00
Andrew Zonenberg 3fc1b9f3fd Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells. 2017-08-28 22:18:57 -07:00
Andrew Zonenberg b5c15636c5 Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass 2017-08-28 22:18:34 -07:00
Andrew Zonenberg c3145863e7 Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused. 2017-08-28 14:25:46 -07:00
Andrew Zonenberg e62362225c Fixed bug causing GP_SPI model to not synthesize 2017-08-27 07:31:48 -07:00
Andrew Zonenberg e6eaf487b6 Fixed more issues with GreenPAK counter sim models 2017-08-15 09:18:36 -07:00
Andrew Zonenberg 3a404be62a Updated PGEN model to have level triggered reset (matches actual hardware behavior 2017-08-15 09:18:27 -07:00
Andrew Zonenberg e5109847c9 Fixed bug in GP_COUNTx model 2017-08-15 09:18:17 -07:00
Andrew Zonenberg 66b256d40e Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high 2017-08-15 09:18:07 -07:00
Clifford Wolf 2cf0b5c157 Merge pull request #381 from azonenberg/countfix 
Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
 2017-08-14 21:47:26 +02:00
Robert Ou 78fd24f40f coolrunner2: Add INVERT parameter to some BUFGs 2017-08-14 12:13:33 -07:00
Robert Ou 1e3ffd57cb coolrunner2: Add FFs with clock enable to cells_sim.v 2017-08-14 12:13:25 -07:00
Andrew Zonenberg 348acbd968 Fixed typo in GP_COUNT8 sim model 2017-08-14 10:45:40 -07:00
Andrew Zonenberg c205d571df Fixed typo in error message 2017-08-14 10:45:40 -07:00
Andrew Zonenberg 0a6c702c41 Changed LEVEL resets for GP_COUNTx to be properly synthesizeable 2017-08-14 10:45:40 -07:00
Andrew Zonenberg 9f3dc59ffe Changed LEVEL resets to be edge triggered anyway 2017-08-14 10:45:40 -07:00
Andrew Zonenberg b049ead042 Added level-triggered reset support to GP_COUNTx simulation models 2017-08-14 10:45:40 -07:00
Andrew Zonenberg ac75524f69 Fixed undeclared "count" in GP_COUNT8_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg db20e3f1c2 Fixed undeclared "count" in GP_COUNT14_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 3618ca2218 Fixed typo in last commit 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4da1a327c0 Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else. 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4504dd78e9 Fixed typo in COUNT8 model 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 60dd5dba7b Moved GP_POR out of digital cells b/c it has delays 2017-08-14 10:45:39 -07:00
Andrew Zonenberg f55d4cc2fd Improved cells_sim_digital model for GP_COUNT8 2017-08-14 10:45:39 -07:00
Andrew Zonenberg fe3a932cfa Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital 2017-08-14 10:45:39 -07:00
Clifford Wolf 8a69759306 Add techlibs/xilinx/lut2lut.v 2017-07-10 12:09:05 +02:00
Clifford Wolf 621787a9e0 Fix some c++ clang compiler errors 2017-07-03 19:38:30 +02:00
Clifford Wolf 5c1c126374 Apply minor coding style changes to coolrunner2 target 2017-07-03 19:35:40 +02:00
Clifford Wolf 6afee022ad Merge pull request #352 from rqou/master 
Initial Coolrunner-II support
 2017-07-03 19:33:36 +02:00
Robert Ou b102c0e254 coolrunner2: Add a few more primitives 
These cannot be inferred yet, but add them to cells_sim.v for now
 2017-06-25 23:58:28 -07:00
Robert Ou 36b75dfcb7 coolrunner2: Initial mapping of latches 2017-06-25 23:58:28 -07:00
Robert Ou 4af5baab21 coolrunner2: Initial mapping of DFFs 
All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
 2017-06-25 23:58:28 -07:00
Robert Ou 1eb5dee799 coolrunner2: Remove redundant INVERT_PTC 2017-06-25 23:58:28 -07:00
Robert Ou ffff001008 coolrunner2: Remove debug prints 2017-06-25 23:58:28 -07:00
Robert Ou 5798105d47 coolrunner2: Correctly handle $_NOT_ after $sop 2017-06-25 23:58:28 -07:00
Robert Ou 908ce3fdce coolrunner2: Also construct the XOR cell in the macrocell 2017-06-25 23:58:28 -07:00
Robert Ou a64b56648d coolrunner2: Initial techmapping for $sop 2017-06-25 23:58:22 -07:00
Andrew Zonenberg cbdddc3af9 greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included 2017-06-24 14:54:07 -07:00
Robert Ou 6e0fb889fa coolrunner2: Initial commit 2017-06-24 07:22:56 -07:00
Clifford Wolf e7a984a4df Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
Andrew Zonenberg 184bd148c9 greenpak4_counters: Added support for parallel output from GP_COUNTx cells 2017-05-22 19:39:55 -07:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
dh73 c27dcc1e47 Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs 2017-04-05 23:01:29 -05:00
Clifford Wolf f3324ed0cc Merge branch 'master' of github.com:cliffordwolf/yosys 2017-02-25 13:08:27 +01:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Andrew Zonenberg 6fed2dc996 Merge https://github.com/cliffordwolf/yosys 2017-02-14 08:29:37 -08:00
Clifford Wolf 2a311c2c38 Fix double-call of log_pop() in synth_greenpak4 2017-02-14 11:57:54 +01:00
Andrew Zonenberg 0d7e71f7ab Merge https://github.com/cliffordwolf/yosys 2017-02-08 22:12:29 -08:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Andrew Zonenberg 27a626ce98 greenpak4: Added POUT to GP_COUNTx cells 2017-01-01 00:56:20 -08:00
Andrew Zonenberg ada98844b9 greenpak4: Added INT pin to GP_SPI 2016-12-21 11:35:29 +08:00
Andrew Zonenberg 6b526e9382 greenpak4: removed unused MISO pin from GP_SPI 2016-12-21 11:33:32 +08:00
Andrew Zonenberg 638f3e3b12 greenpak4: Removed SPI_BUFFER parameter 2016-12-20 13:07:49 +08:00
Andrew Zonenberg 073e8df9f1 greenpak4: replaced MOSI/MISO with single one-way SDAT pin 2016-12-20 12:34:56 +08:00
Andrew Zonenberg d4a05b499e greenpak4: Changed port names on GP_SPI for clarity 2016-12-20 10:30:38 +08:00
Andrew Zonenberg eb80ec84aa greenpak4: Initial implementation of GP_SPI cell 2016-12-20 09:58:02 +08:00
Andrew Zonenberg de1d81511a greenpak4: Updated GP_DCMP cell model 2016-12-17 12:01:22 +08:00
Andrew Zonenberg 7cdba8432c greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF. 2016-12-16 15:14:20 +08:00
Andrew Zonenberg bea6e2f11f greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed interface to GP_DCMPMUX 2016-12-15 15:19:35 +08:00
Andrew Zonenberg 3690aa556c greenpak4: More fixups of GP_DCMPx cells 2016-12-15 07:19:08 +08:00
Andrew Zonenberg 3491d33863 greenpak4: And another typo :( 2016-12-15 07:17:07 +08:00
Andrew Zonenberg ea787e6be3 greenpak4: Fixed another typo 2016-12-15 07:16:26 +08:00
Andrew Zonenberg 58da621ac3 greenpak4: Fixed typo 2016-12-15 07:15:38 +08:00
Andrew Zonenberg 262f8f913c greenpak4: Cleaned up trailing spaces in cells_sim 2016-12-14 14:14:45 +08:00
Andrew Zonenberg c77e6e6114 greenpak4: Added GP_DCMPREF / GP_DCMPMUX 2016-12-14 14:14:26 +08:00
Andrew Zonenberg c3c2983d12 Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF 2016-12-11 10:04:00 +08:00
Andrew Zonenberg 8f3d1f8fcf greenpak4: Added support for inferred input/output inverters on latches 2016-12-10 19:58:32 +08:00
Andrew Zonenberg c53a33143e greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) 2016-12-10 18:46:36 +08:00
Andrew Zonenberg 797c03997e greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency 2016-12-10 13:57:37 +08:00
Andrew Zonenberg 8767cdcac9 Added GP_DLATCH and GP_DLATCHI 2016-12-05 23:49:06 -08:00
Andrew Zonenberg 981f014301 Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet. 2016-12-05 21:22:41 -08:00
Andrew Zonenberg e6ab00d419 Updated help text for synth_greenpak4 2016-12-05 20:11:37 -08:00
Clifford Wolf e9d73d2ee0 Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
Clifford Wolf 3db2ac4e00 Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00
Clifford Wolf 81bdf0ad0f iCE40 flow is not experimental anymore 2016-11-01 11:32:02 +01:00
Clifford Wolf cae5131bac Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00
Andrew Zonenberg 1cca1563c6 Fixed typo in last commit 2016-10-18 20:46:49 -07:00
Andrew Zonenberg e78fa157a3 greenpak4: Added GP_PGEN cell definition 2016-10-18 20:42:44 -07:00
Andrew Zonenberg 091d32b563 Added GLITCH_FILTER parameter to GP_DELAY 2016-10-18 19:53:19 -07:00
Andrew Zonenberg a818472f0c greenpak4: added model for GP_EDGEDET block 2016-10-18 19:33:26 -07:00
Andrew Zonenberg d6feb4b43e greenpak4: Changed parameters for GP_SYSRESET 2016-10-16 22:53:43 -07:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 76352c99c9 Added "prep -nokeepdc" 2016-09-30 17:02:52 +02:00
Clifford Wolf 2ee9bf10d0 Added "prep -nomem" 2016-08-30 23:57:24 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf d77a914683 Added "wreduce -memx" 2016-08-20 12:52:50 +02:00
Clifford Wolf 15ef608453 Added memory_memx pass, "memory -memx", and "prep -memx" 2016-08-19 19:48:26 +02:00
Clifford Wolf 5d90a5b905 Added greenpak4_dffinv 2016-08-15 09:33:06 +02:00
Andrew Zonenberg 0b0ba96488 greenpak4: Changed name of inverted output ports for consistency 2016-08-14 00:30:45 -07:00
Andrew Zonenberg 3b9756c6a3 greenpak4: Added GP_DFFxI cells 2016-08-14 00:11:44 -07:00
Andrew Zonenberg 2b062c48cb greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6) 2016-08-13 22:27:58 -07:00
whitequark 0515809448 synth_greenpak4: use attrmvcp to move LOC from wires to cells. 2016-08-10 20:09:35 +00:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Andrew Zonenberg 52a738a544 Added GP_DAC cell 2016-07-11 22:45:55 -07:00
Andrew Zonenberg baae472b83 Removed VOUT port of GP_BANDGAP 2016-07-11 22:45:42 -07:00
Andrew Zonenberg 8619d33114 Removed splitnets in prep for new gp4par parser 2016-07-11 22:42:25 -07:00
Clifford Wolf cdb58f68ab Added "prep -auto-top" and "synth -auto-top" 2016-07-11 11:40:55 +02:00
whitequark c0645839fe greenpak4: add GP_COUNT{8,14}_ADV cells. 2016-07-10 15:46:46 +00:00
Clifford Wolf 21659847a7 Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations 2016-07-08 14:41:36 +02:00
Clifford Wolf df5ebfa0a0 Improved ice40_ffinit error reporting 2016-06-30 09:58:13 +02:00
Clifford Wolf ca91bccb6b Added "deminout" 2016-06-19 13:08:16 +02:00
Clifford Wolf 95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf 99edf24966 Added "nlutmap -assert" 2016-06-09 11:47:41 +02:00
Clifford Wolf 52b0b4e31e Do not run "wreduce" in "prep -ifx" 2016-06-08 12:14:32 +02:00
Clifford Wolf 2032e6d8e4 Added "proc_mux -ifx" 2016-06-06 17:15:50 +02:00
Andrew Zonenberg 47eace0b9f Added GP_DELAY cell 2016-05-07 21:29:26 -07:00
Andrew Zonenberg 41bbad4e4c Fixed typo in port name 2016-05-07 21:14:42 -07:00
Andrew Zonenberg b5171541cd Fixed extra semicolon 2016-05-07 21:14:18 -07:00
Andrew Zonenberg 85ee88b0ee Fixed typo in parameter name 2016-05-07 21:14:00 -07:00
Andrew Zonenberg a0c19aae55 Added simulation timescale declaration 2016-05-07 21:13:47 -07:00
Clifford Wolf 6fe3d5a1cf Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
Clifford Wolf 126da0ad3d Fixed ice40_opt lut unmapping, added "ice40_opt -unlut" 2016-05-06 14:32:32 +02:00
Andrew Zonenberg 2096a05ec2 Changed order of passes for better handling of INIT attributes on "output reg" FFs 2016-05-04 17:13:54 -07:00
Andrew Zonenberg dee1c27a19 Renamed module parameter 2016-05-04 17:03:45 -07:00
Andrew Zonenberg a613f171ae Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract 2016-05-04 15:55:16 -07:00
Andrew Zonenberg deb1eccab5 Fixed incorrect signal naming in GP_IOBUF 2016-05-04 08:06:18 -07:00
Andrew Zonenberg dcee3256d5 Added tri-state I/O extraction for GreenPak 2016-05-03 22:53:29 -07:00
Andrew Zonenberg 66095153fd Added GreenPak I/O buffer cells 2016-05-03 22:03:04 -07:00
Andrew Zonenberg 9fc9d5f1fb Added comment to clarify GP_ABUF cell 2016-05-02 20:29:39 -07:00
Andrew Zonenberg 79460208c9 Added GP_ABUF cell 2016-05-02 20:27:41 -07:00
Andrew Zonenberg 134e093e4e Added GP_PGA cell 2016-04-27 23:07:21 -07:00
Andrew Zonenberg d57c85111f Merge https://github.com/cliffordwolf/yosys 2016-04-24 22:11:56 -07:00
Andrew Zonenberg 349d717202 Removed VIN_BUF_EN 2016-04-24 17:01:21 -07:00
Andrew Zonenberg 6e215f374d Renamed VOUT to OUT on GP_ACMP cell 2016-04-23 22:53:49 -07:00
Andrew Zonenberg 512486dcf3 Added GP_ACMP cell 2016-04-23 22:33:36 -07:00
Clifford Wolf 09ffebb995 Added "prep -flatten" and "synth -flatten" 2016-04-24 00:48:33 +02:00
Clifford Wolf 77aa2031e7 Converted "prep" to ScriptPass 2016-04-24 00:48:06 +02:00
Clifford Wolf c9c5192cd6 Run clean after splitnets in synth_greenpak4 2016-04-23 23:09:45 +02:00
Clifford Wolf 34195f281f Merge https://github.com/azonenberg/yosys 2016-04-23 10:33:32 +02:00
Clifford Wolf f85cfa5666 Added "shregmap" to synth_greenpak4 2016-04-23 10:31:19 +02:00
Clifford Wolf a24021ea20 Converted synth_greenpak4 to ScriptPass 2016-04-23 10:27:33 +02:00
Andrew Zonenberg 0cbe70eaa4 Fixed typo 2016-04-22 19:08:19 -07:00
Andrew Zonenberg ab11f2aa70 Merge https://github.com/cliffordwolf/yosys 2016-04-22 19:07:55 -07:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Andrew Zonenberg d90c1e9522 Added GP_VREF cell 2016-04-20 20:48:19 -07:00
Andrew Zonenberg d0aaf8d262 Added GP_SHREG cell 2016-04-13 23:13:51 -07:00
Andrew Zonenberg cdefa60367 Refactoring: alphabetized cells_sim 2016-04-13 23:13:39 -07:00
Andrew Zonenberg f1679936fe Fixed missing semicolon 2016-04-09 01:18:02 -07:00
Andrew Zonenberg 58d8715681 Added GP_RCOSC cell 2016-04-09 01:17:13 -07:00
Andrew Zonenberg 01a5f71187 Fixed assertion failure for non-inferrable counters in some cases 2016-04-06 23:42:22 -07:00
Andrew Zonenberg 48c10d90f4 Added second divider to GP_RINGOSC 2016-04-06 23:10:34 -07:00
Andrew Zonenberg 1df559c706 Added GP_RINGOSC primitive 2016-04-06 22:40:25 -07:00
Andrew Zonenberg c2b909c051 Added GP_POR 2016-04-04 21:46:07 -07:00
Andrew Zonenberg c01ff05fab Added GP_BANDGAP cell 2016-04-04 16:56:43 -07:00
Andrew Zonenberg 34667ded53 Removed more debug prints 2016-04-01 23:41:03 -07:00
Andrew Zonenberg 87e7cd9fbd Removed forgotten debug code 2016-04-01 23:39:32 -07:00
Andrew Zonenberg 2386885f22 Added GreenPak inverter support 2016-04-01 21:18:29 -07:00
Andrew Zonenberg 6dbcf50fa1 Added support for inferring counters with asynchronous resets. Fixed use-after-free in inference pass. 2016-04-01 18:07:59 -07:00
Andrew Zonenberg f277267916 Merge https://github.com/cliffordwolf/yosys 2016-04-01 00:03:00 -07:00
Andrew Zonenberg 736a998a75 DFFINIT is now correctly called for all kinds of flipflop, not just DFF 2016-03-31 23:16:45 -07:00
Andrew Zonenberg 7498ff8041 Fixed incorrect port name in cells_map.v 2016-03-31 22:51:22 -07:00
Clifford Wolf 2553319081 Added ScriptPass helper class for script-like passes 2016-03-31 11:16:34 +02:00
Andrew Zonenberg c04a3d2763 Fixed typo (wasn't written in 2012) 2016-03-30 23:58:45 -07:00
Clifford Wolf ec93680bd5 Renamed opt_share to opt_merge 2016-03-31 08:52:49 +02:00
Clifford Wolf 1d0f0d668a Renamed opt_const to opt_expr 2016-03-31 08:46:56 +02:00
Clifford Wolf d31c968d76 Fixed typo in greenpak4_counters.cc 2016-03-31 08:00:59 +02:00
Andrew Zonenberg 984561c034 Renamed counters pass to greenpak4_counters 2016-03-30 22:52:01 -07:00
Andrew Zonenberg 1ae33344f4 Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now. 2016-03-30 22:40:14 -07:00
Andrew Zonenberg 94a6923e7d Updated tech lib for greenpak4 counter with some clarifications 2016-03-30 20:30:25 -07:00
Andrew Zonenberg 489caf32c5 Initial work on greenpak4 counter extraction. Doesn't work but a decent start 2016-03-30 01:07:20 -07:00
Andrew Zonenberg 3ea6026648 Added splitnets to synth_greenpak4 2016-03-29 20:02:59 -07:00
Clifford Wolf 19c20235b5 Added more cell help messages 2016-03-29 15:14:43 +02:00
Clifford Wolf 8c8b2e72b1 Fixed indenting in techlibs/greenpak4/gp_dff.lib 2016-03-29 13:44:14 +02:00
Andrew Zonenberg 75f0030458 Added keep constraint to GP_SYSRESET cell 2016-03-28 23:16:43 -07:00
Andrew Zonenberg ea9cc03092 Added GP_SYSRESET block 2016-03-28 22:49:46 -07:00
Andrew Zonenberg 3197b6c372 Added GP_COUNT8/GP_COUNT14 cells 2016-03-26 23:29:02 -07:00
Andrew Zonenberg 31a7567aff Changed GP_LFOSC parameter configuration 2016-03-26 14:13:52 -07:00
Andrew Zonenberg 44fd3cd149 Added GP_LFOSC cell 2016-03-26 13:42:53 -07:00
Andrew Zonenberg af15b92c86 Renamed GP4_V* cells to GP_V* for consistency 2016-03-26 13:42:41 -07:00
Clifford Wolf b4bf787f10 Added GP_DFFS, GP_DFFR, and GP_DFFSR 2016-03-23 08:46:10 +01:00
Clifford Wolf 456c10f16e Added GP_DFF INIT parameter 2016-03-23 08:12:54 +01:00
Clifford Wolf ca8f8e30f2 Improvements in synth_greenpak4, added -part option 2016-03-21 09:44:52 +01:00
Clifford Wolf ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
Clifford Wolf a75f94ec4a Run dffsr2dff in synth_xilinx 2016-02-13 08:20:19 +01:00
Clifford Wolf 0ccfb88728 Work around DDR dout sim glitches in ice40 SB_IO sim model 2016-02-07 11:19:48 +01:00
Clifford Wolf d69395ca08 Added dffsr2dff 2016-02-02 17:19:01 +01:00
Clifford Wolf bd10927f45 Progress in cell library documentation 2016-02-01 13:58:10 +01:00
Clifford Wolf 17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping 2016-02-01 12:40:32 +01:00
Clifford Wolf 2ee608246f Re-run ice40_opt in "synth_ice40 -abc2" 2015-12-22 12:19:11 +01:00
Clifford Wolf 3102ffbb83 Improvements in ice40_opt 2015-12-22 12:18:38 +01:00
Clifford Wolf 8bf452c364 Bugfix in ice40_ffinit 2015-12-22 12:18:06 +01:00
Clifford Wolf ec93d258a4 Improved ice40_ffinit 2015-12-22 11:15:25 +01:00
Clifford Wolf f1b959dc69 Run opt_const before check in default scripts 2015-12-22 11:15:05 +01:00
Clifford Wolf 494e5f24f9 Added "synth_ice40 -abc2" 2015-12-08 11:16:26 +01:00
Clifford Wolf 4d0a6dac7b Merge pull request #108 from cseed/master 
Added LO to ICESTORM_LC for LUT cascade route.
 2015-12-07 03:32:20 +01:00
Cotton Seed 9f5b6e4cbc Added LO to ICESTORM_LC for LUT cascade route. 2015-12-06 17:24:48 -05:00
Clifford Wolf 0793f1b196 Added ice40_ffinit pass 2015-11-26 18:11:06 +01:00
Clifford Wolf 8ff229a3ea Fixed WE/RE usage in iCE40 BRAM mapping 2015-11-24 10:51:34 +01:00
Clifford Wolf 3ad742056b Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling 2015-11-06 17:02:16 +01:00
Clifford Wolf 864808992b Bugfix in Xilinx LUT mapping 2015-10-30 13:58:03 +01:00
Clifford Wolf bbcbf739e6 Progress on cell help messages 2015-10-20 16:49:11 +02:00
Clifford Wolf 5d1c0ce7c0 Progress on cell help messages 2015-10-17 02:35:19 +02:00
Clifford Wolf 25c1f6e605 Added "prep" command 2015-10-14 22:46:41 +02:00
Clifford Wolf 87adb523aa Added more cell descriptions 2015-10-14 20:30:59 +02:00
Clifford Wolf 7d3a3a3173 Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Clifford Wolf f42218682d Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf 598a475724 Added nlutmap 2015-09-18 21:57:34 +02:00
Clifford Wolf 745d56149d Renamed GreenPAK4 cells, improved GP4 DFF mapping 2015-09-18 12:00:37 +02:00
Clifford Wolf d9cecabb87 Fixed copy&paste typo in synth_greenpak4 2015-09-16 09:39:31 +02:00
Clifford Wolf c5352f45c3 Added GreenPAK4 skeleton 2015-09-16 09:28:37 +02:00
Clifford Wolf 99ccb3180d Fixed ice40 handling of negclk RAM40 2015-09-10 17:35:19 +02:00
Clifford Wolf c475deec6c Switched to Python 3 2015-08-22 09:59:33 +02:00
Clifford Wolf 9596fe74de Another bugfix for ice40 and xilinx brams_init make rules 2015-08-16 21:39:34 +02:00
Clifford Wolf aedcfd6fd3 Fixed Makefile rules for generated share files 2015-08-16 21:15:07 +02:00
Clifford Wolf d5b1a90b33 Added $tribuf and $_TBUF_ sim models 2015-08-16 13:05:32 +02:00
Clifford Wolf 9c33172ece Added tribuf command 2015-08-16 12:55:25 +02:00
Clifford Wolf ff50bc2ac3 Added $tribuf and $_TBUF_ cell types 2015-08-16 12:54:52 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf c43f38c81b Improved handling of "keep" attributes in hierarchical designs in opt_clean 2015-08-12 14:10:14 +02:00
Marcus Comstedt c9e56bc428 Added iCE40 WARMBOOT cell 2015-08-06 22:58:17 +02:00
Clifford Wolf 8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf 516e8828f2 Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) 2015-07-27 22:44:01 +02:00
Clifford Wolf c6ca4780e2 iCE40 DFF sim models: init Q regs to 0 2015-07-20 13:05:18 +02:00
Clifford Wolf 54588a276a Avoid tristate warning for blackbox ice40/cells_sim.v 2015-07-18 11:59:04 +02:00
Clifford Wolf 85aaf08e53 Improved liberty file test case 2015-07-06 17:45:56 +02:00
Clifford Wolf f0c9a099d2 Added "synth -nofsm" 2015-07-02 15:25:38 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf df0163cd2b iCE40: set min bram efficiency to 2% 2015-06-20 09:31:19 +02:00
Clifford Wolf ed128b82d7 Added "synth -nordff -noalumacc" 2015-06-15 17:07:40 +02:00
Clifford Wolf 9500b564ac synth_ice40 now flattens by default 2015-06-09 20:28:17 +02:00
Clifford Wolf 09ef279b60 Added iCE40 PLL cells 2015-05-31 13:10:43 +02:00
Clifford Wolf c329233f0d Added output args to synth_ice40 2015-05-26 17:08:53 +02:00
Clifford Wolf 313f570fcc improved ice40 SB_IO sim model 2015-05-23 10:17:03 +02:00
Clifford Wolf 264eb8eb6e Added ice40 SB_IO sim model 2015-05-23 09:30:24 +02:00
Clifford Wolf 61512b6f41 Verific build fixes 2015-05-17 08:19:52 +02:00
Clifford Wolf 9d067fecea ice40_opt bugfix 2015-04-27 11:36:13 +02:00
Clifford Wolf 310fde197e iCE40: SB_CARRY const fold -> unmap SB_LUT 2015-04-27 10:27:50 +02:00
Clifford Wolf 794d22969d Added simplemap $lut support 2015-04-27 10:16:07 +02:00
Clifford Wolf 8d4a675f91 Added iCE40 const folding support for SB_CARRY 2015-04-27 08:38:14 +02:00
Clifford Wolf 752851954b Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
Clifford Wolf b4d7a590e8 initialized iCE40 brams (mode 0) 2015-04-25 20:44:51 +02:00
Clifford Wolf 4cc4400514 improved iCE40 SB_RAM40_4K simulation model 2015-04-25 20:01:37 +02:00
Clifford Wolf 82a4722f46 More iCE40 bram improvements 2015-04-25 18:04:57 +02:00
Clifford Wolf 687f5a5b12 iCE40 bram progress 2015-04-24 15:38:11 +02:00
Clifford Wolf 308a59aa18 iCE40 bram tests and fixes 2015-04-24 08:32:07 +02:00
Clifford Wolf d6f7698f59 Added ice40 bram support 2015-04-24 00:06:50 +02:00
Clifford Wolf 1277d1bcb8 iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models 2015-04-19 21:37:40 +02:00
Clifford Wolf 49ef830464 added sync reset to ice40 test_ffs.sh 2015-04-18 09:41:31 +02:00
Clifford Wolf f564a65851 Added ice40 test_arith 2015-04-18 09:33:34 +02:00
Clifford Wolf f78fa718be Added ice40 SB_CARRY support 2015-04-18 09:33:08 +02:00
Clifford Wolf 661b647559 Added mapping of synchronous set/reset to iCE40 flow 2015-04-17 11:54:25 +02:00
Clifford Wolf 31755ed1cf Changed ice40 ICESTORM_CARRYCONST port name 2015-04-16 12:09:14 +02:00
Clifford Wolf dc30b034f7 Fixed "dff2dffe -direct-match" 2015-04-16 11:47:59 +02:00
Clifford Wolf 3e9e6e1c22 Added simple ice40 dff tests 2015-04-16 11:31:15 +02:00
Clifford Wolf 0d344a23d3 improved ice40 dff cell mapping 2015-04-16 11:30:56 +02:00
Clifford Wolf 4529c56cc6 use "hierarchy -auto-top" in synth_ice40 2015-04-14 13:45:15 +02:00
Clifford Wolf 06ce496f8d more cells in ice40 cell library 2015-04-14 13:44:43 +02:00
Clifford Wolf 3481f46d1e Improved xilinx "bram1" test 2015-04-09 17:12:12 +02:00
Clifford Wolf 7319951145 Added memory_bram "make_outreg" feature 2015-04-09 16:08:54 +02:00
Clifford Wolf 229825e1b8 Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 13:37:07 +02:00
Clifford Wolf b00cad81d7 Towards DRAM support in Xilinx flow 2015-04-09 08:17:14 +02:00
Clifford Wolf 8520b7fbe0 Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00