Clifford Wolf
2d2c1617ee
Add sf2 techmap rules for more FF types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 15:47:54 -08:00
Clifford Wolf
78762316aa
Refactor SF2 iobuf insertion, Add clkint insertion
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 00:41:02 -08:00
Clifford Wolf
da5181a3df
Improvements in SF2 flow and demo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 20:36:00 -08:00
Clifford Wolf
bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream
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Changes required for VPR place and route in synth_xilinx
2019-03-05 15:33:19 -08:00
Clifford Wolf
724576a4e2
Merge pull request #850 from daveshah1/ecp5_warn_conflict
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ecp5: Demote conflicting FF init values to a warning
2019-03-05 15:23:01 -08:00
Clifford Wolf
13844c7658
Use "write_edif -pvector bra" for Xilinx EDIF files
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 15:16:13 -08:00
Keith Rothman
228f132ec3
Revert BRAM WRITE_MODE changes.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-04 09:22:22 -08:00
David Shah
777864d02e
ecp5: Demote conflicting FF init values to a warning
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-04 11:26:20 +00:00
Keith Rothman
3e16f75bc6
Revert FF models to include IS_x_INVERTED parameters.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:41:21 -08:00
Keith Rothman
5ebeca12eb
Use singular for disabling of DRAM or BRAM inference.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:35:14 -08:00
Keith Rothman
eccaf101d8
Modify arguments to match existing style.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54
Changes required for VPR place and route synth_xilinx.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:02:27 -08:00
Miodrag Milanovic
ca2b3feed8
Fix ECP5 cells_sim for iverilog
2019-03-01 19:25:23 +01:00
Clifford Wolf
a82a7eb42e
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 20:27:27 -08:00
Elms
cd2902ab1f
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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EBLIF output .param will only use necessary 2 bits
Signed-off-by: Elms <elms@freshred.net>
2019-02-28 16:23:40 -08:00
Larry Doolittle
e2fc18f27b
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
Clifford Wolf
41e5028f98
Merge pull request #794 from daveshah1/ecp5improve
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ECP5 Improvements
2019-02-28 14:46:56 -08:00
Eddie Hung
1da0909662
Remove SRL16/32 from cells_xtra
2019-02-28 13:56:45 -08:00
Eddie Hung
73ddab6960
Add SRL16 and SRL32 sim models
2019-02-28 13:56:22 -08:00
Eddie Hung
8aab7fe7e6
Fix SRL16/32 techmap off-by-one
2019-02-28 13:56:00 -08:00
Eddie Hung
fe4d6898de
synth_xilinx to call shregmap with enable support
2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0
synth_xilinx to use shregmap with -params too
2019-02-28 10:21:05 -08:00
Eddie Hung
c9ab18889a
synth_xilinx to now have shregmap call after dff2dffe
2019-02-28 09:32:29 -08:00
Eddie Hung
c29f0c5048
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
2019-02-28 09:31:24 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Larry Doolittle
7a40294e93
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
2019-02-26 09:40:46 -08:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
David Shah
fa2f595cfa
ecp5: Compatibility with Migen AsyncResetSynchronizer
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-25 13:24:30 +00:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress
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Improve ABC netname preservation
2019-02-22 01:16:34 +01:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Clifford Wolf
2fe1c830eb
Bugfix in ice40_dsp
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:28:46 +01:00
Eddie Hung
45ddd9066e
synth to take -abc9 argument
2019-02-20 11:08:49 -08:00
Clifford Wolf
84999a7e68
Add ice40 test_dsp_map test case generator
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 17:18:59 +01:00
Clifford Wolf
218e9051bb
Add "synth_ice40 -dsp"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:42:27 +01:00
Clifford Wolf
7bf4e4a185
Improve iCE40 SB_MAC16 model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 12:55:20 +01:00
Eddie Hung
f9af902532
Merge branch 'master' into xaig
2019-02-19 14:20:04 -08:00
David Shah
bb56cb738d
ecp5: Add DDRDLLA
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 19:34:37 +00:00
David Shah
c36f15b489
ecp5: Add DELAYF/DELAYG blackboxes
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 14:10:43 +00:00
Clifford Wolf
62493c91b2
Add first draft of functional SB_MAC16 model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-19 14:47:27 +01:00
Eddie Hung
323dd0e608
synth_ice40 to have new -abc9 arg
2019-02-14 13:19:27 -08:00
David Shah
e0bc190879
ecp5: Add ECLKSYNCB blackbox
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-13 11:23:25 +00:00
David Shah
7913baedd8
ecp5: Full set of IO-related blackboxes
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-12 12:04:41 +00:00
Eddie Hung
e8f4dc739c
Cope WIDTH of ff/latch cells is default of zero
2019-02-06 15:51:12 -08:00
Eddie Hung
742b4e01b4
Add INIT parameter to all ff/latch cells
2019-02-06 14:16:26 -08:00
David Shah
95789c6136
ecp5: Use abc -dress
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
David Shah
7ef2333497
ice40: Use abc -dress in synth_ice40
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
Miodrag Milanovic
0de328da8f
Fixed Anlogic simulation model
2019-01-25 19:25:25 +01:00
David Shah
549b8e74b2
ecp5: Support for flipflop initialisation
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-22 16:02:56 +00:00
David Shah
ee8c9e854f
ecp5: Add LSRMODE to flipflops for PRLD support
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:35:22 +00:00
David Shah
d8003e87d1
ecp5: More blackboxes
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:34:34 +00:00
David Shah
01ea72f53a
ecp5: Increase threshold for ALU mapping
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:33:47 +00:00
Clifford Wolf
db5765b443
Add SF2 IO buffer insertion
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 14:38:37 +01:00
Clifford Wolf
841ca74c90
Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 13:33:45 +01:00
Clifford Wolf
e041ae3c6d
Merge pull request #777 from mmicko/achronix_cell_sim_fix
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Fix cells_sim.v for Achronix FPGA
2019-01-04 15:18:18 +01:00
Miodrag Milanovic
50ef4561d4
Fix cells_sim.v for Achronix FPGA
2019-01-04 15:15:23 +01:00
Miodrag Milanovic
3b17c9018a
Unify usage of noflatten among architectures
2019-01-04 11:37:25 +01:00
Clifford Wolf
56ca1e6afc
Merge pull request #755 from Icenowy/anlogic-dram-init
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anlogic: implement DRAM initialization
2019-01-02 16:28:18 +01:00
Clifford Wolf
979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init
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Initialization of Anlogic DFFs
2019-01-02 15:52:22 +01:00
Clifford Wolf
da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut
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synth: add k-LUT mode
2019-01-02 15:44:57 +01:00
Clifford Wolf
00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut
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cmp2lut: new techmap pass
2019-01-02 15:43:10 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
17b2831356
synth_ice40: use 4-LUT coarse synthesis mode.
2019-01-02 08:25:55 +00:00
whitequark
18174202a9
synth: add k-LUT mode.
2019-01-02 08:25:03 +00:00
whitequark
fdff32dd73
synth: improve script documentation. NFC.
2019-01-02 08:05:44 +00:00
whitequark
a91892bba4
cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
Clifford Wolf
e09e49ca54
Merge pull request #766 from Icenowy/anlogic-latches
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anlogic: add latch cells
2018-12-31 15:52:01 +01:00
Larry Doolittle
ebe9351f82
Fix 7 instances of add_share_file to add_gen_share_file
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in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
2018-12-29 12:53:12 +01:00
Icenowy Zheng
1b36944299
anlogic: add latch cells
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Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-25 22:47:46 +08:00
Icenowy Zheng
90d00182cf
anlogic: implement DRAM initialization
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As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.
Now add the support by add a new pass to determine unknown values in the
initial value.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-20 07:56:15 +08:00
Clifford Wolf
93d44bb9a6
Merge pull request #752 from Icenowy/anlogic-lut-cost
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Anlogic: let LUT5/6 have more cost than LUT4-
2018-12-19 19:52:31 +01:00
Clifford Wolf
c98d44ac12
Merge pull request #753 from Icenowy/anlogic-makefile-fix
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anlogic: fix Makefile.inc
2018-12-19 19:51:10 +01:00
Icenowy Zheng
3993ba71f7
anlogic: fix Makefile.inc
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During the addition of DRAM inferring support, the installation of
eagle_bb.v is accidentally removed.
Fix this issue.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-19 10:23:58 +08:00
Icenowy Zheng
c9513c695a
Anlogic: let LUT5/6 have more cost than LUT4-
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According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.
So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.
Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-19 09:36:53 +08:00
Icenowy Zheng
4bf8ac728c
anlogic: set the init value of DFFs
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As dffinit has already supported for different initialization strings
for DFFs and check for re-initialization, initialization of Anlogic
DFFs are now ready to go.
Support for set the init values of Anlogic DFFs.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:16:37 +08:00
Icenowy Zheng
7854d5ba21
anlogic: fix dbits of Anlogic Eagle DRAM16X4
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The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.
Fix the dbits number in the RAM configuration.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 14:38:44 +08:00
Icenowy Zheng
d53a2bd1d3
anlogic: add support for Eagle Distributed RAM
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The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.
Enable to synthesis to DRAM.
As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
Icenowy Zheng
634d7d1c14
Revert "Leave only real black box cells"
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This reverts commit 43030db5ff
.
For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
Clifford Wolf
5fa5dbbdda
Rename "fine:" label to "map:" in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 16:36:19 +01:00
Clifford Wolf
2a681909df
Merge pull request #724 from whitequark/equiv_opt
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equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
Clifford Wolf
ceffa66dbd
Merge pull request #730 from smunaut/ffssr_dont_touch
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ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-16 15:50:42 +01:00
Clifford Wolf
0c69f1d777
Merge pull request #725 from olofk/ram4k-init
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Only use non-blocking assignments of SB_RAM40_4K for yosys
2018-12-16 15:42:04 +01:00
Sylvain Munaut
add6ab9b2a
ice40: Honor the "dont_touch" attribute in FFSSR pass
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This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-08 22:46:28 +01:00
whitequark
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
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This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
Olof Kindgren
889297c62a
Only use non-blocking assignments of SB_RAM40_4K for yosys
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In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.
Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.
This patch will change to use non-blocking assignments only for yosys
2018-12-06 21:45:59 +01:00
whitequark
6e559ee3c7
synth_ice40: split `map_gates` off `fine`.
2018-12-06 12:04:39 +00:00
whitequark
d9fa4387c9
synth_ice40: add -noabc option, to use built-in LUT techmapping.
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This should be combined with -relut to get sensible results.
2018-12-05 17:13:46 +00:00
whitequark
9ef078848a
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
whitequark
12596b5003
Fix typo.
2018-12-05 17:13:27 +00:00
Clifford Wolf
e115303129
Merge pull request #713 from Diego-HR/master
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Changes in GoWin synth commands and ALU primitive support
2018-12-05 09:08:30 -08:00
Clifford Wolf
1a260ce89b
Merge pull request #712 from mmicko/anlogic-support
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Initial support for Anlogic FPGA
2018-12-05 09:08:04 -08:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
ea4870b126
synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
2018-12-05 16:30:37 +00:00
whitequark
1719aa88ac
Extract ice40_unlut pass from ice40_opt.
...
Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
2018-12-05 16:30:24 +00:00
Diego H
819ca73096
Changes in GoWin synth commands and ALU primitive support
2018-12-03 20:08:35 -06:00
Miodrag Milanovic
43030db5ff
Leave only real black box cells
2018-12-02 11:57:50 +01:00
Miodrag Milanovic
83bce9f59c
Initial support for Anlogic FPGA
2018-12-01 18:28:54 +01:00
Sylvain Munaut
3e5ab50a73
ice40: Add option to only use CE if it'd be use by more than X FFs
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Clifford Wolf
dbc4cb8f4a
Merge pull request #697 from eddiehung/xilinx_ps7
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Add support for PS7 block for Xilinx
2018-11-12 09:09:22 +01:00
Clifford Wolf
317cc9c2b7
Merge pull request #695 from daveshah1/ecp5_bb
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ecp5: Adding some blackbox cells
2018-11-12 09:08:49 +01:00
Eddie Hung
99a14b0e37
Add support for Xilinx PS7 block
2018-11-10 12:45:07 -08:00
David Shah
fae3e645a2
ecp5: Add 'fake' DCU parameters
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-09 18:25:42 +00:00
David Shah
960c8794fa
ecp5: Add blackboxes for ancillary DCU cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-09 15:18:30 +00:00
David Shah
1f51332808
ecp5: Adding some blackbox cells
...
Signed-off-by: David Shah <dave@ds0.me>
2018-11-07 14:56:38 +00:00
Clifford Wolf
d084fb4c3f
Fix sf2 LUT interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-31 15:36:53 +01:00
Clifford Wolf
cf79fd4376
Basic SmartFusion2 and IGLOO2 synthesis support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-31 15:28:57 +01:00
David Shah
b65932edc4
ecp5: Remove DSP parameters that don't work
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-22 16:20:38 +01:00
David Shah
101f5234ff
ecp5: Add DSP blackboxes
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-21 19:27:02 +01:00
David Shah
d29b517fef
ecp5: Sim model fixes
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 15:16:40 +01:00
David Shah
677b8ed3ca
ecp5: Add latch inference
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 15:16:40 +01:00
Clifford Wolf
24a5c65856
Merge pull request #657 from mithro/xilinx-vpr
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xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
2018-10-18 10:54:03 +02:00
David Shah
df4bfa0ad6
ecp5: Disable LSR inversion
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-16 12:48:39 +01:00
David Shah
812538a036
BRAM improvements
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-12 14:22:21 +01:00
David Shah
bdfead8c64
ecp5: Adding BRAM maps for all size options
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 17:18:17 +01:00
David Shah
983fb7ff88
ecp5: First BRAM type maps successfully
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 16:35:19 +01:00
David Shah
2ef1af8b58
ecp5: Script for BRAM IO connections
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 16:11:00 +01:00
David Shah
346cbbdbdc
ecp5: Adding BRAM initialisation and config
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-09 14:19:04 +01:00
Tim 'mithro' Ansell
b111ea1228
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
...
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
2018-10-08 16:52:12 -07:00
David Shah
31e22c8b96
ecp5: Add blackbox for DP16KD
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-05 11:35:59 +01:00
Clifford Wolf
5f1fea08d5
Add inout ports to cells_xtra.v
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-04 11:30:55 +02:00
Tim Ansell
ad975fb694
xilinx: Adding missing inout IO port to IOBUF
2018-10-03 16:38:32 -07:00
Clifford Wolf
76baae4b94
Merge pull request #645 from daveshah1/ecp5_dram_fix
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ecp5: Don't map ROMs to DRAM
2018-10-02 10:00:10 +02:00
David Shah
fcd39e1398
ecp5: Don't map ROMs to DRAM
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-01 18:34:41 +01:00
Clifford Wolf
51f1bbeeb0
Add iCE40 SB_SPRAM256KA simulation model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-10 11:57:24 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
David Shah
3a3558acce
ecp5: Fixing miscellaneous sim model issues
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 15:56:12 +02:00
David Shah
e9ef077266
ecp5: Fixing 'X' issues with LUT simulation models
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 15:20:34 +02:00
David Shah
b2c62ff8ef
ecp5: ECP5 synthesis fixes
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 14:33:13 +02:00
David Shah
459d367913
ecp5: Adding synchronous set/reset support
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-14 16:18:01 +02:00
David Shah
241429abac
ecp5: Add DRAM match rule
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 16:25:52 +02:00
David Shah
4a60bc83ab
ecp5: Cells and mappings fixes
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 16:14:08 +02:00
David Shah
b0fea67cc6
ecp5: Fixing arith_map
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 15:49:59 +02:00
David Shah
11c916840d
ecp5: Initial arith_map implementation
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 15:46:12 +02:00
David Shah
c2d7be140a
ecp5: Adding basic synth_ecp5 based on synth_ice40
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:52:25 +02:00
David Shah
eb8f3f7dc4
ecp5: Adding DFF maps
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:32:23 +02:00
David Shah
1def34f2a6
ecp5: Adding DRAM map
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:08:42 +02:00
David Shah
b1b9e23f94
ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:27:24 +02:00
David Shah
cd65eeb3b3
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:09:18 +02:00
Clifford Wolf
57fc8dd582
Add "synth_ice40 -json"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-13 13:35:10 +02:00
Clifford Wolf
83631555dd
Fix ice40_opt for cases where a port is connected to a signal with width != 1
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-11 18:12:42 +02:00
Clifford Wolf
7fecc3c199
Make -nordff the default in "prep"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-30 13:17:09 +02:00
Olof Kindgren
faac2c5595
Avoid mixing module port declaration styles in ice40 cells_sim.v
...
The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
2018-05-17 13:54:43 +02:00
Clifford Wolf
47eb150eec
Merge pull request #537 from mithro/yosys-vpr
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Improving Yosys when used with VPR
2018-05-04 12:32:30 +02:00
Clifford Wolf
b4c1d3084f
Add "synth_intel --noiopads"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-30 13:02:56 +02:00
Tim 'mithro' Ansell
d6bdefd2e9
Improving vpr output support.
...
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
2018-04-18 16:55:12 -07:00
Tim 'mithro' Ansell
ca39e493ba
synth_ice40: Rework the vpr blif output slightly.
2018-04-18 16:55:08 -07:00
Clifford Wolf
81a457c4a6
Add "synth_ice40 -nodffe"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-16 20:44:26 +02:00
c60k28
efed2420d6
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
Robert Ou
14e49fb057
coolrunner2: Add an ANDTERM/XOR between chained FFs
...
In some cases (e.g. the low bits of counters) the design might end up
with a flip-flop whose input is directly driven by another flip-flop.
This isn't possible in the Coolrunner-II architecture, so add a single
AND term and XOR in this case.
2018-03-31 03:54:48 -07:00
Robert Ou
cfa3753b89
coolrunner2: Split multi-bit nets
...
The PAR tool doesn't expect any "dangling" nets with no drivers nor
sinks. By splitting the nets, clean removes them.
2018-03-31 02:56:11 -07:00
Robert Ou
8fe9cdf364
coolrunner2: Add extraction for TFFs
2018-03-31 02:54:26 -07:00
Larry Doolittle
efaef82f75
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
Clifford Wolf
6991c132b5
Add Xilinx RAM64X1D and RAM128X1D simulation models
2018-03-07 17:31:48 +01:00
Clifford Wolf
27dd500d31
Add "synth -noshare"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 17:13:45 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Robert Ou
2abcd98527
coolrunner2: Move LOC attributes onto the IO cells
2018-01-17 16:17:32 -08:00
Clifford Wolf
9ac560f5d3
Add "dffinit -highlow" and fix synth_intel
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-09 18:42:19 +01:00
Clifford Wolf
b66d50e62d
Fix minor typo in "prep" help message
2017-12-19 21:44:05 +01:00
Graham Edgecombe
f93e6637aa
Fix port names in SB_IO_OD
2017-12-10 15:33:38 +00:00
Graham Edgecombe
52ace35a73
Remove trailing comma from SB_IO_OD port list
...
This isn't compatible with Icarus Verilog.
2017-12-10 15:33:38 +00:00
Tim Ansell
3cc31f197c
Fix spelling in -vpr help for synth_ice40
2017-12-08 18:44:45 -08:00
Clifford Wolf
1f6e8f86c5
Merge pull request #462 from daveshah1/up5k
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Add remaining UltraPlus cells to ice40 techlib
2017-11-28 15:53:53 +01:00
David Shah
5e8d1922a4
Add remaining UltraPlus cells to ice40 techlib
2017-11-28 11:07:49 +00:00
Clifford Wolf
4782d59a3f
Merge pull request #455 from daveshah1/up5k
...
Add UltraPlus specific cells to ice40 techlib
2017-11-18 19:12:48 +01:00
David Shah
0505f1043c
Remove unnecessary keep attributes
2017-11-18 17:53:21 +00:00
Clifford Wolf
c01df04e32
Merge pull request #453 from dh73/master
...
Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
2017-11-18 09:56:36 +01:00
David Shah
8ae73e60e2
Merge branch 'master' into up5k
2017-11-17 15:15:39 +00:00
Clifford Wolf
234726c655
Add "synth_ice40 -vpr"
2017-11-16 21:37:02 +01:00
David Shah
f9f3ca5da0
Add some UltraPlus cells to ice40 techlib
2017-11-16 12:24:35 +00:00
dh73
3fd1d61e2a
Initial Cyclone 10 support
2017-11-08 22:45:21 -06:00
dh73
1fc061d90c
Organizing Speedster file names
2017-11-08 20:23:55 -06:00
Larry Doolittle
50bcd9a728
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
Clifford Wolf
65f91e5120
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
2017-10-03 17:31:21 +02:00
dh73
4718e65763
Tested and working altsyncarm without init files
2017-10-01 19:59:45 -05:00
dh73
cbaba62401
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
2017-10-01 11:04:17 -05:00
Clifford Wolf
c5b204d8d2
Add first draft of eASIC back-end
2017-09-29 17:53:43 +02:00
Clifford Wolf
e64b9d5a4d
Fix synth_ice40 doc regarding -top default
2017-09-29 17:52:57 +02:00
Andrew Zonenberg
122532b7e1
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
2017-09-14 10:26:32 -07:00
Andrew Zonenberg
a84172b23b
Initial support for extraction of counters with clock enable
2017-09-14 10:26:10 -07:00
Clifford Wolf
2f75240e36
Merge pull request #406 from azonenberg/coolrunner-techmap
...
Coolrunner techmapping improvements
2017-09-02 13:43:51 +02:00
Robert Ou
5f65e24ccb
coolrunner2: Finish fixing special-use p-terms
2017-09-01 07:22:16 -07:00
Robert Ou
fa04366f38
coolrunner2: Generate a feed-through AND term when necessary
2017-09-01 07:22:01 -07:00
Robert Ou
6775177171
coolrunner2: Initial fixes for special p-terms
...
Certain signals can only be controlled by a product term and not a
sum-of-products. Do the initial work for fixing this.
2017-09-01 07:21:51 -07:00
Robert Ou
7f08be4304
coolrunner2: Fix mapping of flip-flops
2017-09-01 07:21:39 -07:00
Robert Ou
ac84f47829
coolrunner2: Combine some for loops together
2017-09-01 07:21:31 -07:00
Andrew Zonenberg
40021d2fd8
Fixed typo in error message
2017-09-01 06:45:10 -07:00
Andrew Zonenberg
fc0c7f74dc
Added blackbox $__COUNT_ cell model
2017-09-01 06:44:28 -07:00
Andrew Zonenberg
80aaf50302
Refactoring: moved modules still in cells_sim to cells_sim_wip
2017-09-01 06:44:15 -07:00
Andrew Zonenberg
06754108fc
Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction
2017-08-30 16:40:41 -07:00
Andrew Zonenberg
634f18be96
extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
2017-08-30 16:28:25 -07:00
Andrew Zonenberg
3fc1b9f3fd
Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.
2017-08-28 22:18:57 -07:00
Andrew Zonenberg
b5c15636c5
Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass
2017-08-28 22:18:34 -07:00
Andrew Zonenberg
c3145863e7
Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused.
2017-08-28 14:25:46 -07:00
Andrew Zonenberg
e62362225c
Fixed bug causing GP_SPI model to not synthesize
2017-08-27 07:31:48 -07:00
Andrew Zonenberg
e6eaf487b6
Fixed more issues with GreenPAK counter sim models
2017-08-15 09:18:36 -07:00
Andrew Zonenberg
3a404be62a
Updated PGEN model to have level triggered reset (matches actual hardware behavior
2017-08-15 09:18:27 -07:00
Andrew Zonenberg
e5109847c9
Fixed bug in GP_COUNTx model
2017-08-15 09:18:17 -07:00
Andrew Zonenberg
66b256d40e
Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high
2017-08-15 09:18:07 -07:00
Clifford Wolf
2cf0b5c157
Merge pull request #381 from azonenberg/countfix
...
Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
2017-08-14 21:47:26 +02:00
Robert Ou
78fd24f40f
coolrunner2: Add INVERT parameter to some BUFGs
2017-08-14 12:13:33 -07:00
Robert Ou
1e3ffd57cb
coolrunner2: Add FFs with clock enable to cells_sim.v
2017-08-14 12:13:25 -07:00
Andrew Zonenberg
348acbd968
Fixed typo in GP_COUNT8 sim model
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
c205d571df
Fixed typo in error message
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
0a6c702c41
Changed LEVEL resets for GP_COUNTx to be properly synthesizeable
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
9f3dc59ffe
Changed LEVEL resets to be edge triggered anyway
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
b049ead042
Added level-triggered reset support to GP_COUNTx simulation models
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
ac75524f69
Fixed undeclared "count" in GP_COUNT8_ADV
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
db20e3f1c2
Fixed undeclared "count" in GP_COUNT14_ADV
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
3618ca2218
Fixed typo in last commit
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
4da1a327c0
Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else.
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
4504dd78e9
Fixed typo in COUNT8 model
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
60dd5dba7b
Moved GP_POR out of digital cells b/c it has delays
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
f55d4cc2fd
Improved cells_sim_digital model for GP_COUNT8
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
fe3a932cfa
Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
2017-08-14 10:45:39 -07:00
Clifford Wolf
8a69759306
Add techlibs/xilinx/lut2lut.v
2017-07-10 12:09:05 +02:00
Clifford Wolf
621787a9e0
Fix some c++ clang compiler errors
2017-07-03 19:38:30 +02:00
Clifford Wolf
5c1c126374
Apply minor coding style changes to coolrunner2 target
2017-07-03 19:35:40 +02:00
Clifford Wolf
6afee022ad
Merge pull request #352 from rqou/master
...
Initial Coolrunner-II support
2017-07-03 19:33:36 +02:00
Robert Ou
b102c0e254
coolrunner2: Add a few more primitives
...
These cannot be inferred yet, but add them to cells_sim.v for now
2017-06-25 23:58:28 -07:00
Robert Ou
36b75dfcb7
coolrunner2: Initial mapping of latches
2017-06-25 23:58:28 -07:00
Robert Ou
4af5baab21
coolrunner2: Initial mapping of DFFs
...
All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
2017-06-25 23:58:28 -07:00
Robert Ou
1eb5dee799
coolrunner2: Remove redundant INVERT_PTC
2017-06-25 23:58:28 -07:00
Robert Ou
ffff001008
coolrunner2: Remove debug prints
2017-06-25 23:58:28 -07:00
Robert Ou
5798105d47
coolrunner2: Correctly handle $_NOT_ after $sop
2017-06-25 23:58:28 -07:00
Robert Ou
908ce3fdce
coolrunner2: Also construct the XOR cell in the macrocell
2017-06-25 23:58:28 -07:00
Robert Ou
a64b56648d
coolrunner2: Initial techmapping for $sop
2017-06-25 23:58:22 -07:00
Andrew Zonenberg
cbdddc3af9
greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included
2017-06-24 14:54:07 -07:00
Robert Ou
6e0fb889fa
coolrunner2: Initial commit
2017-06-24 07:22:56 -07:00
Clifford Wolf
e7a984a4df
Add dff2ff.v techmap file
2017-05-31 11:45:58 +02:00
Andrew Zonenberg
184bd148c9
greenpak4_counters: Added support for parallel output from GP_COUNTx cells
2017-05-22 19:39:55 -07:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
dh73
c27dcc1e47
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
2017-04-05 23:01:29 -05:00
Clifford Wolf
f3324ed0cc
Merge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 13:08:27 +01:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Andrew Zonenberg
6fed2dc996
Merge https://github.com/cliffordwolf/yosys
2017-02-14 08:29:37 -08:00
Clifford Wolf
2a311c2c38
Fix double-call of log_pop() in synth_greenpak4
2017-02-14 11:57:54 +01:00
Andrew Zonenberg
0d7e71f7ab
Merge https://github.com/cliffordwolf/yosys
2017-02-08 22:12:29 -08:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Andrew Zonenberg
27a626ce98
greenpak4: Added POUT to GP_COUNTx cells
2017-01-01 00:56:20 -08:00
Andrew Zonenberg
ada98844b9
greenpak4: Added INT pin to GP_SPI
2016-12-21 11:35:29 +08:00
Andrew Zonenberg
6b526e9382
greenpak4: removed unused MISO pin from GP_SPI
2016-12-21 11:33:32 +08:00
Andrew Zonenberg
638f3e3b12
greenpak4: Removed SPI_BUFFER parameter
2016-12-20 13:07:49 +08:00
Andrew Zonenberg
073e8df9f1
greenpak4: replaced MOSI/MISO with single one-way SDAT pin
2016-12-20 12:34:56 +08:00
Andrew Zonenberg
d4a05b499e
greenpak4: Changed port names on GP_SPI for clarity
2016-12-20 10:30:38 +08:00
Andrew Zonenberg
eb80ec84aa
greenpak4: Initial implementation of GP_SPI cell
2016-12-20 09:58:02 +08:00
Andrew Zonenberg
de1d81511a
greenpak4: Updated GP_DCMP cell model
2016-12-17 12:01:22 +08:00
Andrew Zonenberg
7cdba8432c
greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
2016-12-16 15:14:20 +08:00
Andrew Zonenberg
bea6e2f11f
greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed interface to GP_DCMPMUX
2016-12-15 15:19:35 +08:00
Andrew Zonenberg
3690aa556c
greenpak4: More fixups of GP_DCMPx cells
2016-12-15 07:19:08 +08:00
Andrew Zonenberg
3491d33863
greenpak4: And another typo :(
2016-12-15 07:17:07 +08:00