Eddie Hung
671cca59a9
Missing abc_flop_q attribute on SPRAM
2019-04-17 14:44:08 -07:00
Eddie Hung
437fec0d88
Map to SB_LUT4 from fastest input first
2019-04-17 13:01:17 -07:00
Eddie Hung
58847df1b9
Mark seq output ports with "abc_flop_q" attr
2019-04-17 12:27:45 -07:00
Eddie Hung
1eade06671
Also update Makefile.inc
2019-04-17 12:27:02 -07:00
Eddie Hung
4fb9ccfcd8
synth_ice40 to use renamed files
2019-04-17 12:22:03 -07:00
Eddie Hung
42c33db22c
Rename to abc.*
2019-04-17 12:15:34 -07:00
Eddie Hung
c1ebe51a75
Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"
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This reverts commit a7632ab332
.
2019-04-17 11:10:20 -07:00
Eddie Hung
a7632ab332
Try using an ICE40_CARRY_LUT primitive to avoid ABC issues
2019-04-17 11:10:04 -07:00
Eddie Hung
17fb6c3522
Fix spacing
2019-04-17 08:40:50 -07:00
Eddie Hung
743c164eee
Add SB_LUT4 to box library
2019-04-16 17:34:11 -07:00
Eddie Hung
7980118d74
Add ice40 box files
2019-04-16 16:39:30 -07:00
Eddie Hung
cbb85e40e8
Add MUXCY and XORCY to cells_box.v
2019-04-16 14:53:28 -07:00
Eddie Hung
aece97024d
Fix spacing
2019-04-16 13:16:20 -07:00
Eddie Hung
53b19ab1f5
Make cells.box whiteboxes not blackboxes
2019-04-16 12:43:14 -07:00
Eddie Hung
5189695362
read_verilog cells_box.v before techmap
2019-04-16 12:41:56 -07:00
Eddie Hung
d259e6dc14
synth_xilinx: before abc read +/xilinx/cells_box.v
2019-04-16 11:21:46 -07:00
Eddie Hung
3ac4977b70
Add +/xilinx/cells_box.v containing models for ABC boxes
2019-04-16 11:21:03 -07:00
Eddie Hung
8c6cf07acf
Revert "Add abc_box_id attribute to MUXF7/F8 cells"
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This reverts commit 8fbbd9b129
.
2019-04-16 11:14:59 -07:00
Eddie Hung
8fbbd9b129
Add abc_box_id attribute to MUXF7/F8 cells
2019-04-15 22:25:09 -07:00
Eddie Hung
538592067e
Merge branch 'xaig' into xc7mux
2019-04-15 22:04:20 -07:00
Diego
f9272fc56d
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
2019-04-12 23:40:02 -05:00
Eddie Hung
04e466d5e4
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-12 12:28:37 -07:00
Eddie Hung
f77da46a87
Merge remote-tracking branch 'origin/master' into xaig
2019-04-12 12:21:48 -07:00
Eddie Hung
db1a5ec6a2
Merge pull request #928 from litghost/add_xc7_sim_models
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Add additional cells sim models for core 7-series primitives.
2019-04-12 11:52:45 -07:00
Eddie Hung
8228b593ef
Merge remote-tracking branch 'origin/master' into xc7mux
2019-04-12 09:46:07 -07:00
Keith Rothman
1f9235ede5
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-12 09:35:15 -07:00
Diego
643ae9bfc5
Fixing issues in CycloneV cell sim
2019-04-11 19:59:03 -05:00
Eddie Hung
233edf00fe
Fix cells_map.v some more
2019-04-11 10:48:14 -07:00
Eddie Hung
8658b56a08
More fine tuning
2019-04-11 10:08:05 -07:00
Eddie Hung
0ec8564099
Fix cells_map.v
2019-04-11 10:04:58 -07:00
Eddie Hung
bca3779657
Fix typo
2019-04-11 09:25:19 -07:00
Eddie Hung
87b8d29a90
Juggle opt calls in synth_xilinx
2019-04-11 09:13:39 -07:00
Eddie Hung
cd7b2de27f
WIP for cells_map.v -- maybe working?
2019-04-10 18:05:09 -07:00
Eddie Hung
3d577586fd
Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
2019-04-10 16:15:23 -07:00
Eddie Hung
3f5dab0d09
Fix for when B_SIGNED = 1
2019-04-10 14:51:10 -07:00
Eddie Hung
32561332b2
Update doc for synth_xilinx
2019-04-10 14:48:58 -07:00
Eddie Hung
17a02df05c
ff_map.v after abc
2019-04-10 12:36:06 -07:00
Eddie Hung
1ec949d5ed
Tidy up
2019-04-10 09:02:42 -07:00
Eddie Hung
526aef9c2a
Move map_cells to before map_luts
2019-04-10 08:50:31 -07:00
Eddie Hung
e0b46eb4cb
WIP for $shiftx to wide mux
2019-04-10 08:49:55 -07:00
Eddie Hung
4dac9818bd
Update LUT delays
2019-04-10 08:49:39 -07:00
Eddie Hung
9a6da9a79a
synth_* with -retime option now calls abc with -D 1 as well
2019-04-10 08:32:53 -07:00
Eddie Hung
3e368593eb
Add cells.lut to techlibs/xilinx/
2019-04-09 14:33:37 -07:00
Eddie Hung
fd88ab5c83
synth_xilinx to call abc with -lut +/xilinx/cells.lut
2019-04-09 14:32:39 -07:00
Eddie Hung
b9e19071b8
Add delays to cells.box
2019-04-09 14:32:10 -07:00
Keith Rothman
e107ccdde8
Fix LUT6_2 definition.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-09 11:43:19 -07:00
Eddie Hung
f2042fc7c4
synth_xilinx with abc9 to use -box
2019-04-09 11:01:46 -07:00
Eddie Hung
2ae26b986c
Add techlibs/xilinx/cells.box
2019-04-09 10:58:58 -07:00
Eddie Hung
3fc474aa73
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-09 10:06:44 -07:00
Keith Rothman
5e0339855f
Add additional cells sim models for core 7-series primatives.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-09 09:01:53 -07:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Eddie Hung
1d526b7f06
Call shregmap twice -- once for variable, another for fixed
2019-04-05 17:35:49 -07:00
Eddie Hung
a5f33b5409
Move dffinit til after abc
2019-04-05 16:20:43 -07:00
Eddie Hung
0364a5d811
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 15:46:18 -07:00
Eddie Hung
9758701574
Move techamp t:$_DFF_?N? to before abc call
2019-04-05 15:39:05 -07:00
Eddie Hung
23a6533e98
Retry
2019-04-05 15:31:54 -07:00
Eddie Hung
8b6085254a
Resolve @daveshah1 comment, update synth_xilinx help
2019-04-05 15:15:13 -07:00
Eddie Hung
ff0912c75e
synth_xilinx to techmap FFs after abc call, otherwise -retime fails
2019-04-05 14:43:06 -07:00
Eddie Hung
544843da71
techmap inside map_cells stage
2019-04-05 12:55:52 -07:00
Eddie Hung
7b7ddbdba7
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 08:13:34 -07:00
Eddie Hung
e3f20b17af
Missing techmap entry in help
2019-04-04 08:13:10 -07:00
Eddie Hung
2fb02247a7
Use soft-logic, not LUT3 instantiation
2019-04-04 08:10:40 -07:00
Eddie Hung
572603409c
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 07:54:42 -07:00
Eddie Hung
d9cb787391
synth_xilinx to map_cells before map_luts
2019-04-04 07:48:13 -07:00
Eddie Hung
77755b5a66
Cleanup comments
2019-04-04 07:41:40 -07:00
Eddie Hung
736e19f02d
t:$dff* -> t:$dff t:$dffe
2019-04-04 07:39:19 -07:00
Eddie Hung
0e2d929cea
-nosrl meant when -nobram
2019-04-03 08:28:07 -07:00
Eddie Hung
ff385a5ad0
Remove duplicate STARTUPE2
2019-04-03 08:14:09 -07:00
Eddie Hung
88630cd02c
Disable shregmap in synth_xilinx if -retime
2019-04-03 07:14:20 -07:00
Miodrag Milanovic
df92e9bdc2
Make nobram false by default for gowin
2019-04-02 19:21:01 +02:00
Eddie Hung
f9fb05cf66
synth_xilinx to use shregmap with -minlen 3
2019-03-25 13:18:55 -07:00
Eddie Hung
46753cf89f
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 13:10:42 -07:00
David Shah
46f6a60d58
xilinx: Add keep attribute where appropriate
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 13:57:17 +00:00
Eddie Hung
4cc6b3e942
Add '-nosrl' option to synth_xilinx
2019-03-21 15:04:44 -07:00
Eddie Hung
81c207fb9b
Fine tune cells_map.v
2019-03-20 10:55:14 -07:00
Eddie Hung
505e4c2d59
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
2019-03-19 21:58:05 -07:00
Eddie Hung
5445cd4d00
Add support for variable length Xilinx SRL > 128
2019-03-19 17:44:33 -07:00
Eddie Hung
ae2a625d05
Restore original synth_xilinx commands
2019-03-19 16:14:08 -07:00
Eddie Hung
9156e18f92
Fix spacing
2019-03-19 16:12:32 -07:00
Eddie Hung
f239cb821e
Fix INIT for variable length SRs that have been bumped up one
2019-03-19 14:54:43 -07:00
Eddie Hung
24553326dd
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 13:11:30 -07:00
Clifford Wolf
fe1fb1336b
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-19 20:30:28 +01:00
Eddie Hung
fadeadb8c8
Only accept <128 for variable length, only if $shiftx exclusive
2019-03-16 08:51:13 -07:00
Eddie Hung
29a8d4745e
Cleanup synth_xilinx
2019-03-15 23:01:40 -07:00
Eddie Hung
06f8f2654a
Working
2019-03-15 19:13:40 -07:00
Eddie Hung
e7ef7fa443
Reverse bits in INIT parameter for Xilinx, since MSB is shifted first
2019-03-14 09:38:42 -07:00
Eddie Hung
af5706c2a3
Misspell
2019-03-14 09:06:56 -07:00
Eddie Hung
8af9979aab
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
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This reverts commit 26ecbc1aee
.
2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee
Add shregmap -init_msb_first and use in synth_xilinx
2019-03-14 08:10:02 -07:00
Eddie Hung
79b4a275ce
Fix cells_map for SRL
2019-03-14 08:09:48 -07:00
Eddie Hung
edca2f1163
Move shregmap until after first techmap
2019-03-13 17:13:52 -07:00
Eddie Hung
24f129ddfb
Refactor $__SHREG__ in cells_map.v
2019-03-13 16:17:54 -07:00
Clifford Wolf
9284cf92b8
Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:14:18 +01:00
Clifford Wolf
ff4c2a14ae
Fix typo in ice40_braminit help msg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-09 13:24:55 -08:00
Clifford Wolf
2ace1b0041
Merge pull request #859 from smunaut/ice40_braminit
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iCE40 BRAM primitives init from file
2019-03-09 13:24:10 -08:00
Sylvain Munaut
5b6f591033
ice40: Run ice40_braminit pass by default
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
Sylvain Munaut
e71055cfe8
ice40: Add ice40_braminit pass to allow initialization of BRAM from file
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This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
Clifford Wolf
350dfd3745
Add link to SF2 / igloo2 macro library guide
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 09:08:26 -08:00
Clifford Wolf
8b0719d1e3
Improvements in sf2 cells_sim.v
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 16:18:49 -08:00
Clifford Wolf
2d2c1617ee
Add sf2 techmap rules for more FF types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 15:47:54 -08:00
Clifford Wolf
78762316aa
Refactor SF2 iobuf insertion, Add clkint insertion
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 00:41:02 -08:00
Clifford Wolf
da5181a3df
Improvements in SF2 flow and demo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 20:36:00 -08:00
Clifford Wolf
bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream
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Changes required for VPR place and route in synth_xilinx
2019-03-05 15:33:19 -08:00
Clifford Wolf
724576a4e2
Merge pull request #850 from daveshah1/ecp5_warn_conflict
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ecp5: Demote conflicting FF init values to a warning
2019-03-05 15:23:01 -08:00
Clifford Wolf
13844c7658
Use "write_edif -pvector bra" for Xilinx EDIF files
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 15:16:13 -08:00
Keith Rothman
228f132ec3
Revert BRAM WRITE_MODE changes.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-04 09:22:22 -08:00
David Shah
777864d02e
ecp5: Demote conflicting FF init values to a warning
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-04 11:26:20 +00:00
Keith Rothman
3e16f75bc6
Revert FF models to include IS_x_INVERTED parameters.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:41:21 -08:00
Keith Rothman
5ebeca12eb
Use singular for disabling of DRAM or BRAM inference.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:35:14 -08:00
Keith Rothman
eccaf101d8
Modify arguments to match existing style.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54
Changes required for VPR place and route synth_xilinx.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:02:27 -08:00
Miodrag Milanovic
ca2b3feed8
Fix ECP5 cells_sim for iverilog
2019-03-01 19:25:23 +01:00
Clifford Wolf
a82a7eb42e
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 20:27:27 -08:00
Elms
cd2902ab1f
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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EBLIF output .param will only use necessary 2 bits
Signed-off-by: Elms <elms@freshred.net>
2019-02-28 16:23:40 -08:00
Larry Doolittle
e2fc18f27b
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
Clifford Wolf
41e5028f98
Merge pull request #794 from daveshah1/ecp5improve
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ECP5 Improvements
2019-02-28 14:46:56 -08:00
Eddie Hung
1da0909662
Remove SRL16/32 from cells_xtra
2019-02-28 13:56:45 -08:00
Eddie Hung
73ddab6960
Add SRL16 and SRL32 sim models
2019-02-28 13:56:22 -08:00
Eddie Hung
8aab7fe7e6
Fix SRL16/32 techmap off-by-one
2019-02-28 13:56:00 -08:00
Eddie Hung
fe4d6898de
synth_xilinx to call shregmap with enable support
2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0
synth_xilinx to use shregmap with -params too
2019-02-28 10:21:05 -08:00
Eddie Hung
c9ab18889a
synth_xilinx to now have shregmap call after dff2dffe
2019-02-28 09:32:29 -08:00
Eddie Hung
c29f0c5048
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
2019-02-28 09:31:24 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Larry Doolittle
7a40294e93
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
2019-02-26 09:40:46 -08:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
David Shah
fa2f595cfa
ecp5: Compatibility with Migen AsyncResetSynchronizer
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-25 13:24:30 +00:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress
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Improve ABC netname preservation
2019-02-22 01:16:34 +01:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Clifford Wolf
2fe1c830eb
Bugfix in ice40_dsp
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:28:46 +01:00
Eddie Hung
45ddd9066e
synth to take -abc9 argument
2019-02-20 11:08:49 -08:00
Clifford Wolf
84999a7e68
Add ice40 test_dsp_map test case generator
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 17:18:59 +01:00
Clifford Wolf
218e9051bb
Add "synth_ice40 -dsp"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:42:27 +01:00
Clifford Wolf
7bf4e4a185
Improve iCE40 SB_MAC16 model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 12:55:20 +01:00
Eddie Hung
f9af902532
Merge branch 'master' into xaig
2019-02-19 14:20:04 -08:00
David Shah
bb56cb738d
ecp5: Add DDRDLLA
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 19:34:37 +00:00
David Shah
c36f15b489
ecp5: Add DELAYF/DELAYG blackboxes
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 14:10:43 +00:00
Clifford Wolf
62493c91b2
Add first draft of functional SB_MAC16 model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-19 14:47:27 +01:00
Eddie Hung
323dd0e608
synth_ice40 to have new -abc9 arg
2019-02-14 13:19:27 -08:00
David Shah
e0bc190879
ecp5: Add ECLKSYNCB blackbox
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-13 11:23:25 +00:00
David Shah
7913baedd8
ecp5: Full set of IO-related blackboxes
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-12 12:04:41 +00:00
Eddie Hung
e8f4dc739c
Cope WIDTH of ff/latch cells is default of zero
2019-02-06 15:51:12 -08:00
Eddie Hung
742b4e01b4
Add INIT parameter to all ff/latch cells
2019-02-06 14:16:26 -08:00
David Shah
95789c6136
ecp5: Use abc -dress
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
David Shah
7ef2333497
ice40: Use abc -dress in synth_ice40
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
Miodrag Milanovic
0de328da8f
Fixed Anlogic simulation model
2019-01-25 19:25:25 +01:00
David Shah
549b8e74b2
ecp5: Support for flipflop initialisation
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-22 16:02:56 +00:00
David Shah
ee8c9e854f
ecp5: Add LSRMODE to flipflops for PRLD support
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:35:22 +00:00
David Shah
d8003e87d1
ecp5: More blackboxes
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:34:34 +00:00