Eddie Hung
66ff0511a0
Add -set_attr option, -unpart to take attr name
2019-11-23 09:52:17 -08:00
Eddie Hung
fb49da21bd
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 08:39:19 -08:00
Eddie Hung
96941aacbb
Do not use log_signal() for empty SigSpec to prevent "{ }"
2019-11-22 23:29:10 -08:00
Eddie Hung
736b96b186
Call submod once, more meaningful submod names, ignore largest domain
2019-11-22 23:16:15 -08:00
Eddie Hung
1851f4b488
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 23:01:18 -08:00
Eddie Hung
d223e11a72
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 22:28:35 -08:00
Eddie Hung
cba3073026
submod to bitty rather bussy, for bussy wires used as input and output
2019-11-22 20:53:58 -08:00
Eddie Hung
900c806d4e
Move clkpart into passes/hierarchy
2019-11-22 17:25:53 -08:00
Eddie Hung
2c5dfd802d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:24:45 -08:00
Eddie Hung
8119383f81
Constant driven signals are also an input to submodules
2019-11-22 17:23:51 -08:00
Eddie Hung
89a4a4d90f
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:04:33 -08:00
Eddie Hung
573396851a
Oops
2019-11-22 17:03:30 -08:00
Eddie Hung
bf7d36627e
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 17:00:35 -08:00
Eddie Hung
95af8f56e4
Only action if there is more than one clock domain
2019-11-22 17:00:11 -08:00
Eddie Hung
00d76f6cc4
Replace TODO
2019-11-22 16:58:08 -08:00
Eddie Hung
0806b8e398
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 16:50:56 -08:00
Eddie Hung
6a52897aee
sigmap(wire) should inherit port_output status of POs
2019-11-22 16:48:11 -08:00
Eddie Hung
698854955c
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:41:48 -08:00
Eddie Hung
84153288bb
Brackets
2019-11-22 15:41:34 -08:00
Eddie Hung
3df191cec5
Entry in Makefile.inc
2019-11-22 15:41:23 -08:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Eddie Hung
856a3dc98d
New 'clkpart' to {,un}partition design according to clock/enable
2019-11-22 15:35:51 -08:00
Clifford Wolf
03fb92ed6f
Add "opt_mem" pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 17:45:22 +01:00
Eddie Hung
c4ec42ac38
When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_
...
Since they should be captured downwards from the owning flop
2019-11-21 16:17:03 -08:00
David Shah
ca99b1ee8d
proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 20:46:41 +00:00
Eddie Hung
729c6b93e8
endomain -> ctrldomain
2019-11-20 14:32:01 -08:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
Marcin Kościelnicki
15232a48af
Fix #1462 , #1480 .
2019-11-19 08:57:39 +01:00
David Shah
7ff5d6d30a
memory_collect: Copy attr from RTLIL::Memory to cell
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-18 13:58:03 +00:00
Marcin Kościelnicki
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
Clifford Wolf
527434de49
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst
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wreduce: Don't trim zeros or sext when not matching ARST_VALUE
2019-11-17 10:42:30 +01:00
David Shah
f5804a84fd
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-14 18:43:15 +00:00
Clifford Wolf
e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname
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Add "autoname" pass and use it in "synth_ice40"
2019-11-14 18:03:44 +01:00
Clifford Wolf
07c854b7af
Add "autoname" pass and use it in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-13 13:41:16 +01:00
whitequark
ab0fb19cff
Merge pull request #1488 from whitequark/flowmap-fixes
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flowmap: fix a few crashes
2019-11-13 11:57:17 +00:00
Clifford Wolf
4be5a0fd7c
Update fsm_detect bugfix
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-12 17:31:30 +01:00
Clifford Wolf
16df8f5a32
Bugfix in fsm_detect
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-12 14:26:02 +01:00
whitequark
c68722818a
flowmap: when doing mincut, ensure source is always in X, not X̅.
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Fixes #1475 .
2019-11-12 00:15:43 +00:00
whitequark
eef32195bd
flowmap: don't break if that creates a k+2 (and larger) LUT either.
...
Fixes #1405 .
2019-11-11 23:13:00 +00:00
Sean Cross
82f60ba938
Makefile: don't assume python is called `python3`
...
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
Clifford Wolf
b8774ae849
Fix dffmux peepopt init handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 11:40:32 +02:00
Clifford Wolf
bb0851bfc5
Move GENERATE_PATTERN macro to separate utility header
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 11:40:01 +02:00
Clifford Wolf
af61d92441
Disable left-over log_debug in peepopt_dffmux.pmg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 10:43:47 +02:00
Eddie Hung
304e5f9ea4
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 13:03:06 -07:00
Eddie Hung
ea54b5ea61
Revert "Be mindful that sigmap(wire) could have dupes when checking \init"
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This reverts commit f46ac1df9f
.
2019-10-08 12:41:24 -07:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427
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Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-08 12:38:29 -07:00
Eddie Hung
4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
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async2sync to be called by equiv_opt only when -async2sync given
2019-10-08 10:53:44 -07:00
Eddie Hung
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
Eddie Hung
472b5d33a6
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments
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Add notes and comments for xilinx_dsp
2019-10-08 10:53:30 -07:00
Eddie Hung
2cb2116b4c
Use "abc9_period" attribute for delay target
2019-10-07 15:03:44 -07:00
Clifford Wolf
4072a96663
Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry
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Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-06 12:11:20 +02:00
Eddie Hung
3879ca1398
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
Eddie Hung
5c68da4150
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-05 09:27:12 -07:00
Clifford Wolf
10d0bad67e
Update README.md
2019-10-05 18:13:04 +02:00
Eddie Hung
f90a4b1e24
Missed this
2019-10-05 08:57:37 -07:00
Eddie Hung
991c2ca95b
Add comment on why we have to match for clock-enable/reset muxes
2019-10-05 08:56:37 -07:00
Eddie Hung
ebb059896a
Add note on pattern detector
2019-10-05 08:53:01 -07:00
Miodrag Milanović
7c074ef844
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix
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Fixes for MSVC build
2019-10-05 07:48:30 +02:00
Eddie Hung
792cd31052
Add comments for xilinx_dsp_cascade
2019-10-04 22:31:04 -07:00
Eddie Hung
12fd2ec4f0
Improve comments for xilinx_dsp_CREG
2019-10-04 22:31:04 -07:00
Eddie Hung
14e4aeece6
Fix comment
2019-10-04 22:31:04 -07:00
Eddie Hung
8027ebf05b
Restore optimisation for sigM.empty()
2019-10-04 22:31:04 -07:00
Eddie Hung
77d7a5c14a
Retry on fixing TODOs
2019-10-04 22:31:04 -07:00
Eddie Hung
52583ecff8
Revert "Fix TODOs"
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This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
2019-10-04 22:31:04 -07:00
Eddie Hung
6d68972619
More comments, cleanup
2019-10-04 22:31:04 -07:00
Eddie Hung
7de9c33931
Fix TODOs
2019-10-04 22:31:04 -07:00
Eddie Hung
983068103e
Consistency
2019-10-04 22:31:04 -07:00
Eddie Hung
cf82b38478
Add comments for xilinx_dsp
2019-10-04 22:31:04 -07:00
Eddie Hung
a5ac33f230
Merge branch 'master' into eddie/abc_to_abc9
2019-10-04 17:53:20 -07:00
Eddie Hung
f0cadb0de8
Fix from merge
2019-10-04 17:52:19 -07:00
Eddie Hung
bbc0e06af3
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8
Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
2019-10-04 17:35:43 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
74ef8feeaf
Fix xilinx_dsp for unsigned extensions
2019-10-04 16:46:15 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
84f978bdc2
Add -async2sync to help text as per @daveshah1
2019-10-04 10:17:46 -07:00
Miodrag Milanovic
c0b14cfea7
Fixes for MSVC build
2019-10-04 16:29:46 +02:00
Eddie Hung
549d6ea467
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 10:55:23 -07:00
Eddie Hung
a9efd2e81c
Restore part of doc
2019-10-03 10:51:53 -07:00
Eddie Hung
7a6dec1cef
Add new -async2sync option
2019-10-03 10:30:51 -07:00
Eddie Hung
8765ec3c27
Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys"
...
This reverts commit a39505e329
.
2019-10-03 10:07:15 -07:00
Eddie Hung
c6d15c9aad
Revert "Update doc for equiv_opt"
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This reverts commit a274b7cc86
.
2019-10-03 10:07:03 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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Add -select option to aigmap
2019-10-03 11:54:04 +02:00
Clifford Wolf
afdc990595
Merge pull request #1429 from YosysHQ/clifford/checkmapped
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Add "check -mapped"
2019-10-03 11:50:53 +02:00
Clifford Wolf
3e27b2846b
Add "check -allow-tbuf"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-03 11:49:56 +02:00
Eddie Hung
e9645c7fa7
Fix broken CI, check reset even for constants, trim rstmux
2019-10-02 21:26:26 -07:00
Eddie Hung
c6a55d948a
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-02 18:07:38 -07:00
Eddie Hung
d99810ad8a
Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-02 18:01:45 -07:00
Eddie Hung
f46ac1df9f
Be mindful that sigmap(wire) could have dupes when checking \init
2019-10-02 16:08:46 -07:00
Eddie Hung
265a655ef9
Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf
2019-10-02 12:43:35 -07:00
Clifford Wolf
45e4c040d7
Add "check -mapped"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-02 13:35:03 +02:00
Eddie Hung
edc3780723
techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
2019-09-30 17:20:12 -07:00
Eddie Hung
1b96d29174
No need to punch ports at all
2019-09-30 17:02:20 -07:00
Eddie Hung
390b960c8c
Resolve FIXME on calling proc just once
2019-09-30 16:37:29 -07:00
Eddie Hung
e529872b01
Remove need for $currQ port connection
2019-09-30 16:33:40 -07:00
Eddie Hung
f2f19df2d4
Add -select option to aigmap
2019-09-30 15:26:29 -07:00
Eddie Hung
e0aa772663
Add comment
2019-09-30 15:19:02 -07:00
Eddie Hung
a6994c5f16
scc call on active module module only, plus cleanup
2019-09-30 12:57:19 -07:00
Eddie Hung
8684b58bed
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 12:29:35 -07:00
Eddie Hung
a274b7cc86
Update doc for equiv_opt
2019-09-30 10:59:56 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
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Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Clifford Wolf
0d28e45dcb
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync
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equiv_opt to call async2sync when not -multiclock like SymbiYosys
2019-09-30 17:04:21 +02:00
Clifford Wolf
10e57f3880
Fix $dlatch handling in async2sync
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-30 14:58:23 +02:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
5a4011e8c9
Fix "scc" call inside abc9 to consider all wires
2019-09-29 09:58:00 -07:00
Miodrag Milanovic
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Eddie Hung
313d2478e9
Split ABC9 based on clocking only, add "abc_mergeability" attr for en
2019-09-27 18:41:04 -07:00
Eddie Hung
fe722b737c
Add -select option to aigmap
2019-09-27 17:44:01 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Eddie Hung
a39505e329
equiv_opt to call async2sync when not -multiclock like SymbiYosys
2019-09-27 12:59:10 -07:00
Eddie Hung
aebbfffd71
Ooops AREG and BREG to default to -1
2019-09-27 11:57:53 -07:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
...
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Eddie Hung
26657037b8
Update doc with max cascade chain of 20
2019-09-26 14:31:02 -07:00
Eddie Hung
5b9deef10d
Do not always zero out C (e.g. during cascade breaks)
2019-09-26 13:59:05 -07:00
Eddie Hung
95f0dd57df
Update doc
2019-09-26 13:44:41 -07:00
Eddie Hung
58f31096ab
Zero out ports
2019-09-26 13:40:38 -07:00
Eddie Hung
af59856ba1
xilinx_dsp_cascade to also cascade AREG and BREG
2019-09-26 13:29:18 -07:00
Eddie Hung
832216dab0
Try recursive pmgen for P cascade
2019-09-26 12:09:57 -07:00
Eddie Hung
bd8661e024
CREG to check for \keep
2019-09-26 10:32:01 -07:00
Eddie Hung
c0bb1d22e8
Remove newline
2019-09-26 10:31:55 -07:00
Eddie Hung
f1de93edf5
Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)
2019-09-25 22:58:03 -07:00
Eddie Hung
cd8a640989
Reject if (* init *) present
2019-09-25 18:21:08 -07:00
Eddie Hung
aeb1539818
Rework xilinx_dsp postAdd for new wreduce call
2019-09-25 17:22:30 -07:00
Eddie Hung
5f8917c984
Fix memory issue since SigSpec& could be invalidated
2019-09-25 16:45:51 -07:00
Eddie Hung
486dd7c483
unextend only used in init
2019-09-25 14:05:59 -07:00
Eddie Hung
53ea5daa42
Call 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 14:04:36 -07:00
Clifford Wolf
b432c9b44b
Improve "portlist" command
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-25 09:20:38 +02:00
Clifford Wolf
6c427d36dd
Add "portlist" command
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-24 18:08:59 +02:00
Eddie Hung
44374b1b2b
"abc_padding" attr for blackbox outputs that were padded, remove them later
2019-09-23 21:58:40 -07:00
Eddie Hung
e556d48d45
Set [AB]CASCREG to legal values
2019-09-23 16:00:11 -07:00
Eddie Hung
b824a56cde
Comment to explain separating CREG packing
2019-09-23 13:58:10 -07:00
Eddie Hung
15dfbc8125
Separate out CREG packing into new pattern, to avoid conflict with PREG
2019-09-23 13:27:10 -07:00
Eddie Hung
26a6c55665
Move log_debug("\n") later
2019-09-23 13:27:00 -07:00
Eddie Hung
d0dbbc2605
Move unextend initialisation later
2019-09-23 13:26:34 -07:00
Eddie Hung
a67af3d5e5
Use new port() overload once more
2019-09-23 13:00:44 -07:00
Eddie Hung
bcee87a457
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-23 10:58:28 -07:00
N. Engelhardt
3bed4cb18a
fix show command for macos
2019-09-23 17:47:05 +02:00
Eddie Hung
ec08a031b5
Revert abc9.cc
2019-09-20 17:52:23 -07:00
Eddie Hung
72ce06909e
Trim mismatched connection to be same (smallest) size
2019-09-20 17:51:36 -07:00
Eddie Hung
567e5f0aa7
Fix first testcase in #1391
2019-09-20 17:51:27 -07:00
Eddie Hung
53817b8575
Use new port/param overload in pmg
2019-09-20 14:21:22 -07:00
Eddie Hung
d122083a11
Output pattern matcher items as log_debug()
2019-09-20 12:42:28 -07:00
Eddie Hung
95644b00cb
OPMODE is port not param
2019-09-20 12:37:29 -07:00
Eddie Hung
3fb839e255
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 12:21:36 -07:00
Eddie Hung
eb597431f0
Do not run xilinx_dsp_cascadeAB for now
2019-09-20 12:18:37 -07:00
Eddie Hung
0bca366bcd
WIP for xiinx_dsp_cascadeAB
2019-09-20 12:07:14 -07:00
Eddie Hung
b0ad2592be
Run until convergence
2019-09-20 12:04:16 -07:00
Eddie Hung
1b892ca1be
Cleanup ice40_dsp.pmg
2019-09-20 12:03:45 -07:00
Eddie Hung
d88903e610
Cleanup xilinx_dsp
2019-09-20 12:03:25 -07:00
Eddie Hung
1809f463fb
More exceptions
2019-09-20 12:03:10 -07:00
Eddie Hung
70c5444b25
Update doc
2019-09-20 10:07:54 -07:00
Eddie Hung
ed187ef1cf
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
2019-09-20 10:00:09 -07:00
Eddie Hung
1844498c5f
Add an overload for port/param with default value
2019-09-20 09:59:42 -07:00
Eddie Hung
a0d3ecf8c6
Small cleanup
2019-09-20 08:41:28 -07:00
Clifford Wolf
1f64b34c64
Add "add -mod"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 10:27:17 +02:00
Eddie Hung
8cfcaf108e
Disable support for SB_MAC16 reset since it is async
2019-09-19 22:48:57 -07:00
Eddie Hung
a59f80834f
SB_MAC16 ffCD to not pack same as ffO
2019-09-19 22:39:47 -07:00
Eddie Hung
1b88211ec6
Clarify
2019-09-19 21:58:34 -07:00
Eddie Hung
34f9a8ceb2
Update doc for ice40_dsp
2019-09-19 21:57:11 -07:00
Eddie Hung
8a94ce7aa5
Add an index
2019-09-19 20:04:44 -07:00
Eddie Hung
c83a667555
Fix width of D
2019-09-19 18:08:46 -07:00
Eddie Hung
a8bc460805
Use ID() macro
2019-09-19 16:13:22 -07:00
Eddie Hung
b88f0f6450
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
2019-09-19 15:47:41 -07:00
Eddie Hung
37b0fc17e3
Re-enable sign extension for C input
2019-09-19 15:40:17 -07:00
Eddie Hung
64a72ed51e
Do not perform width-checks for DSP48E1 which is much more complicated
2019-09-19 14:50:11 -07:00
Eddie Hung
517ca49963
Remove TODO as check should not be necessary
2019-09-19 14:49:47 -07:00
Eddie Hung
307b2dc8e5
Revert index to select
2019-09-19 14:46:53 -07:00
Eddie Hung
ea5e5a212e
Cleanup xilinx_dsp too
2019-09-19 14:34:06 -07:00
Eddie Hung
1a0f7ed09c
Refactor ce{mux,pol} -> hold{mux,pol}
2019-09-19 14:27:25 -07:00
Eddie Hung
429c9852ce
Add HOLD/RST support for SB_MAC16
2019-09-19 14:02:55 -07:00
Eddie Hung
2766465a2b
Add support for SB_MAC16 CD and H registers
2019-09-19 12:14:33 -07:00
Eddie Hung
c8310a6e76
Refactor ice40_dsp.pmg
2019-09-19 12:00:48 -07:00
Clifford Wolf
b76fac3ac3
Add techmap_autopurge attribute, fixes #1381
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-19 20:00:52 +02:00
Eddie Hung
29d446d758
Cleanup
2019-09-19 10:39:00 -07:00
Marcin Kościelnicki
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
Eddie Hung
70c607d7dd
Document (* gentb_skip *) attr for test_autotb
2019-09-18 12:41:35 -07:00
Eddie Hung
f7dbfef792
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 12:40:21 -07:00
Eddie Hung
b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
...
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
2019-09-18 12:40:08 -07:00
Eddie Hung
44bf4ac35c
Add doc on pattern detector for overflow
2019-09-18 12:35:24 -07:00
Eddie Hung
fd3b033903
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 12:23:22 -07:00
Eddie Hung
347cbf59bd
Check overflow condition is power of 2 without using int32
2019-09-18 12:16:03 -07:00
Eddie Hung
1f18736d20
Add support for overflow using pattern detector
2019-09-18 09:39:59 -07:00
Eddie Hung
0932e23dff
Separate dffrstmux from dffcemux, fix typos
2019-09-18 09:34:42 -07:00
Eddie Hung
2b93b8fc74
Merge pull request #1374 from YosysHQ/eddie/fix1371
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Fix two non-deterministic behaviours that cause divergence between compilers
2019-09-15 13:56:07 -07:00
Eddie Hung
14d72c39c3
Revert "Make one check $shift(x)? only; change testcase to be 8b"
...
This reverts commit e2c2d784c8
.
2019-09-13 16:33:18 -07:00
Eddie Hung
9a73adde50
Explicitly order function arguments
2019-09-13 16:18:05 -07:00
Eddie Hung
95e80809a5
Revert "SigSet<Cell*> to use stable compare class"
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This reverts commit 4ea34aaacd
.
2019-09-13 09:49:15 -07:00
Clifford Wolf
a67d63714b
Fix handling of z_digit "?" and fix optimization of cmp with "z"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-13 13:39:39 +02:00
Eddie Hung
3a39073302
Set more ports explicitly
2019-09-12 17:10:43 -07:00
Eddie Hung
a1123b095c
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-12 12:11:11 -07:00
Eddie Hung
4ea34aaacd
SigSet<Cell*> to use stable compare class
2019-09-12 11:45:02 -07:00
David Shah
6044fff074
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock
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Add equiv_opt -multiclock
2019-09-12 12:26:28 +01:00
Eddie Hung
f3081c20e7
Add support for A1 and B1 registers
2019-09-11 17:16:46 -07:00
Eddie Hung
4369fc17d0
Raise a RuntimeError instead of AssertionError
2019-09-11 17:06:37 -07:00
Eddie Hung
6fa6bf483c
Rename {A,B} -> {A2,B2}
2019-09-11 16:21:24 -07:00
Eddie Hung
3a49aa6b4a
Tidy up
2019-09-11 14:20:49 -07:00
Eddie Hung
817ac7c5e0
Fix UB
2019-09-11 14:18:02 -07:00
Eddie Hung
63431fe42a
Fix UB
2019-09-11 14:17:45 -07:00
Eddie Hung
690b1a064d
Add PCOUT -> PCIN non-shifted cascading
2019-09-11 13:48:45 -07:00
Eddie Hung
c0f26c2da8
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 13:37:11 -07:00
Eddie Hung
bdb5e0f29c
Cope with presence of reset muxes too
2019-09-11 13:36:37 -07:00
Eddie Hung
4937917cd8
Cleanup
2019-09-11 13:22:52 -07:00
Eddie Hung
e9eb855d38
Make unextend a udata
2019-09-11 13:06:49 -07:00
Eddie Hung
bbef0d2ac8
Only display log message if did_something
2019-09-11 12:29:26 -07:00
Eddie Hung
d232e6a6cd
Input registers to add DSP as new siguser to block upstream packing
2019-09-11 11:46:21 -07:00
Eddie Hung
e5bdb521fa
More cleanup
2019-09-11 10:55:45 -07:00
Marcin Kościelnicki
f72765090c
Add -match-init option to dff2dffs.
2019-09-11 19:38:20 +02:00
Eddie Hung
0d709d2bb5
Add support for A/B/C/D/AD reset
2019-09-11 10:15:19 -07:00
Eddie Hung
ded805ae5d
Add support for RSTM
2019-09-11 07:34:14 -07:00
David Shah
c43e52d2d7
Add equiv_opt -multiclock
...
Signed-off-by: David Shah <dave@ds0.me>
2019-09-11 13:55:59 +01:00
David Shah
c7f1368cd2
Merge pull request #1362 from xobs/smtbmc-msvc2-build-fixes
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MSVC2 fixes
2019-09-11 09:57:30 +01:00
Eddie Hung
fc7008671f
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 00:57:25 -07:00
Eddie Hung
edf90afd20
Rename dffmuxext -> dffmux, also remove constants in dff+mux
2019-09-11 00:56:38 -07:00
Eddie Hung
6b23c7c227
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-11 00:07:33 -07:00
Eddie Hung
feb3fa65a3
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-11 00:01:31 -07:00
Eddie Hung
b08797da6b
Only pack out registers if \init is zero or x; then remove \init from PREG
2019-09-10 21:33:14 -07:00
Eddie Hung
37a34eeb04
Fix RSTP
2019-09-10 20:56:13 -07:00
Eddie Hung
af147d1430
Add support for RSTP
2019-09-10 20:51:48 -07:00
Eddie Hung
c6df55a9e7
enpol -> cepol
2019-09-10 18:59:03 -07:00
Eddie Hung
86700c2bea
d?ffmux -> d?ffcemux
2019-09-10 18:52:54 -07:00
Eddie Hung
8b8a68b38a
Refactor MREG and PREG to out_dffe subpattern
2019-09-10 18:27:05 -07:00
Eddie Hung
e64e650f9c
Update help text
2019-09-10 16:35:10 -07:00
Eddie Hung
d30b2a6d7e
Update xilinx_dsp help text
2019-09-10 16:33:13 -07:00
Eddie Hung
cba63fe72b
Oops
2019-09-09 22:06:23 -07:00
Eddie Hung
02cf9933b9
Support subtraction as well
2019-09-09 21:39:42 -07:00
Eddie Hung
31e60353ac
Support TWO24
2019-09-09 21:11:41 -07:00
Eddie Hung
0bb6fd8448
Refactor
2019-09-09 20:58:54 -07:00
Eddie Hung
5a6552e56b
Add initial USE_SIMD=FOUR12 support
2019-09-09 20:57:20 -07:00
Eddie Hung
2c04430445
Only trim sigM if USE_MULT; only look for ffM then too
2019-09-09 20:57:03 -07:00
Eddie Hung
be0eaf3a9a
Fix misspelling
2019-09-09 16:46:33 -07:00
Eddie Hung
6348f9512c
Rename
2019-09-09 16:45:38 -07:00
Eddie Hung
1df9c5d277
Oops
2019-09-09 16:07:40 -07:00
Eddie Hung
5f8f0e1383
Tidy up
2019-09-09 15:59:10 -07:00
Eddie Hung
04bc287271
Refactor using subpattern in_dffe
2019-09-09 15:51:14 -07:00
Sean Cross
8d128ba6d0
passes: opt_share: don't statically initialize mergeable_type_map
...
In 3d3779b037
this got turned from a
`std::map<std::string, std::string>` to `std::map<IdString, IdString>`.
Consequently, this exposed some initialization sequencing issues (#1361 ).
Only initialize the map when it's first used, to avoid these static issues.
This fixes #1361 .
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-09 12:40:01 +08:00
Marcin Kościelnicki
a82e8df7d3
techmap: Add support for extracting init values of ports
2019-09-07 16:30:43 +02:00
Eddie Hung
e2c2d784c8
Make one check $shift(x)? only; change testcase to be 8b
2019-09-06 22:48:23 -07:00
Eddie Hung
74a5c802f7
Pack CREG
2019-09-06 21:01:36 -07:00
Eddie Hung
6a9205280f
Use unextend lambda
2019-09-06 18:40:11 -07:00
Eddie Hung
b69512a5b9
Fix ffP just like ffPmux
2019-09-06 15:51:21 -07:00
Eddie Hung
5344bfe637
Perform D replacement properly
2019-09-06 15:46:15 -07:00
Eddie Hung
74eac76699
Add support for DREG
2019-09-06 15:32:26 -07:00
Eddie Hung
ef56f8596f
Fine tune nusers when postAdd
2019-09-06 15:11:41 -07:00
Eddie Hung
0d1d8b4d24
Fix macc and mul tests
2019-09-06 14:57:36 -07:00
Eddie Hung
8246062acf
Fix enable polarity
2019-09-06 14:36:10 -07:00
Eddie Hung
2c32056990
Logging for ffAD
2019-09-06 14:10:12 -07:00
Eddie Hung
e926f2973e
Add support for pre-adder and AD register
2019-09-06 14:06:57 -07:00
Eddie Hung
ef77162ce4
Document (* gentb_skip *) attr for test_autotb
2019-09-06 13:28:15 -07:00
Eddie Hung
da8fe83f7a
Tidy up ice40_dsp some more
2019-09-06 12:16:40 -07:00
Eddie Hung
776d769941
Use more index patterns
2019-09-06 12:07:35 -07:00
Eddie Hung
a945f6c7ef
Fix ffPmux to cope with offset
2019-09-06 11:58:56 -07:00
Eddie Hung
fbf1b74946
Simplify filter expressions
2019-09-06 11:39:20 -07:00
Eddie Hung
39a5d046ea
Fix nusers condition in ffP
2019-09-06 11:38:19 -07:00
Eddie Hung
cdc1e1f5c2
Check adder is <= 48 bits before packing
2019-09-06 10:35:06 -07:00
Eddie Hung
91f68c4de2
Check nusers for M and P enable muxes
2019-09-06 09:59:35 -07:00
Eddie Hung
4fe24b20f9
More nusers() checks for A and B enable muxes
2019-09-06 09:47:32 -07:00
Eddie Hung
dc10559f31
Cleanup
2019-09-05 21:39:52 -07:00
Eddie Hung
174edbcb96
Sensitive to CEB CEM CEP polarity
2019-09-05 21:38:35 -07:00
Eddie Hung
53ca536d67
ffAmuxAB -> ffAenpol
2019-09-05 21:28:28 -07:00
Eddie Hung
5a2fc6fcb5
Refactor ice40_dsp
2019-09-05 18:06:59 -07:00
Eddie Hung
888ae1d05e
Fix broken ice40_dsp
2019-09-05 17:58:19 -07:00
Eddie Hung
38e73a3788
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-05 13:01:34 -07:00
Eddie Hung
e742478e1d
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-05 13:01:27 -07:00
Eddie Hung
a32b14a55f
Do not check signedness of post-adder (assume taken care of by DSP)
2019-09-05 12:38:47 -07:00
Eddie Hung
903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival
...
Allow arrival times of sequential outputs to be specified to abc9
2019-09-05 12:00:23 -07:00
Eddie Hung
7bd55f379c
Use filter instead of index; support wide enable muxes
2019-09-05 11:55:14 -07:00
Eddie Hung
fe5a1324c9
Do not make ff[MP]mux semioptional, use sigmap
2019-09-05 11:46:38 -07:00
Eddie Hung
447a31e75d
Add support for CEP
2019-09-05 11:00:27 -07:00
Eddie Hung
05282afc25
Add support for CEB, remove check on nusers
2019-09-05 10:46:33 -07:00
Eddie Hung
0166e02e78
Cleanup
2019-09-05 10:07:56 -07:00
Eddie Hung
aa462da395
Support CEA
2019-09-05 10:07:26 -07:00
Clifford Wolf
30f1ac7ce9
Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:51:53 +02:00
Clifford Wolf
694a8f75cf
Add flatten handling of pre-existing wires as created by interfaces, fixes #1145
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:30:58 +02:00
Eddie Hung
09c26c55bb
Get rid of sigBset too
2019-09-04 17:22:02 -07:00
Eddie Hung
91ef4457b0
Get rid of sigAset
2019-09-04 17:18:49 -07:00
Eddie Hung
42548d9790
Get rid of sigPused
2019-09-04 17:06:17 -07:00
Eddie Hung
93d798272d
Compute sigP properly
2019-09-04 16:59:57 -07:00
Eddie Hung
ba629e6a28
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-04 15:36:07 -07:00
Eddie Hung
433b0c677c
Remove log_cell() calls
2019-09-04 13:42:44 -07:00
Eddie Hung
229e54568e
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
2019-09-04 12:37:48 -07:00
Eddie Hung
3732d421c5
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-04 12:37:42 -07:00
Eddie Hung
2b86055848
Add peepopt_dffmuxext
2019-09-04 12:35:15 -07:00
Eddie Hung
e67e4a5ed6
Support CEM
2019-09-04 10:52:51 -07:00
Eddie Hung
80aec0f006
st.ffP from if to assert
2019-09-03 16:37:59 -07:00
Eddie Hung
16316aa05d
Rename muxAB to postAddMux
2019-09-03 16:24:59 -07:00
Eddie Hung
cd002ad3fb
Use choices for addAB, now called postAdd
2019-09-03 16:10:16 -07:00
Eddie Hung
2d80866daf
Add support for load value into DSP48E1.P
2019-09-03 15:53:10 -07:00
Eddie Hung
682153de4b
Process post-adder first since C could be used for load-P
2019-09-03 14:57:59 -07:00
Eddie Hung
97d11708e0
Use feedback path for MACC
2019-09-03 14:37:32 -07:00
Eddie Hung
d2306d7b1d
Adopt @cliffordwolf's suggestion
2019-09-03 12:18:50 -07:00
Eddie Hung
d6a84a78a7
Merge remote-tracking branch 'origin/master' into eddie/deferred_top
2019-09-03 10:49:21 -07:00
Eddie Hung
2fa3857963
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-02 12:13:44 -07:00
Eddie Hung
4aa505d1b2
Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc
...
ice40_dsp to allow signed multipliers
2019-09-01 10:11:33 -07:00
Miodrag Milanovic
fa5065e9b5
Fix select command error msg, fixes issue #1081
2019-09-01 11:00:09 +02:00
Eddie Hung
a09e69dd56
Fine tune xilinx_dsp pattern matcher
2019-08-30 16:18:58 -07:00
Eddie Hung
8f503fe3e6
autoremove ffM
2019-08-30 15:30:04 -07:00
Eddie Hung
e67f049e3b
Remove debug
2019-08-30 15:03:43 -07:00
Eddie Hung
15bab02a1b
ffM before addAB
2019-08-30 15:03:12 -07:00
Eddie Hung
c497114e94
Another oops
2019-08-30 15:02:53 -07:00
Eddie Hung
44a35015b3
Update commented out
2019-08-30 15:01:38 -07:00
Eddie Hung
390cf34d0a
Add support for ffM
2019-08-30 15:00:56 -07:00
Eddie Hung
2983a35dc0
Update comment
2019-08-30 15:00:40 -07:00
Eddie Hung
17b77fd411
Missing dep for test_pmgen
2019-08-30 14:01:07 -07:00
Eddie Hung
89359b6927
Missing dep for test_pmgen
2019-08-30 14:00:40 -07:00
Eddie Hung
723815b384
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-30 13:26:19 -07:00
Eddie Hung
c7f1ccbcb0
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 12:28:35 -07:00
Eddie Hung
999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
...
abc9 to not call "clean" at end of run (often called outside)
2019-08-30 12:27:09 -07:00
Eddie Hung
c1459bc748
Do not restrict multiplier to unsigned
2019-08-30 12:22:14 -07:00
Eddie Hung
4e782f1509
New pmgen requires explicit accept
2019-08-30 11:02:10 -07:00
Eddie Hung
d2d2816f8c
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-30 10:30:54 -07:00
Eddie Hung
f0fef90e9d
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 10:30:46 -07:00
Eddie Hung
295c18bd6b
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-30 09:50:20 -07:00
Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
David Shah
6919c0f9b0
Merge branch 'master' into xc7dsp
2019-08-30 13:57:15 +01:00
Eddie Hung
18cabe9370
Output has priority over input when stitching in abc9
2019-08-29 17:24:03 -07:00
Eddie Hung
3e0f73c3df
abc9 to not call "clean" at end of run (often called outside)
2019-08-29 12:12:59 -07:00
Eddie Hung
1467761060
Fix typo that's gone unnoticed for 5 months!?!
2019-08-29 10:33:28 -07:00
Eddie Hung
c4e5310823
Use a dummy box file if none specified
2019-08-28 20:58:55 -07:00
Eddie Hung
116c249601
-auto-top should check $abstract (deferred) modules with (* top *)
2019-08-28 19:59:25 -07:00
Eddie Hung
4eb5847dbd
Cleanup
2019-08-28 18:10:33 -07:00
Eddie Hung
0af64df10c
Account for D port being a constant
2019-08-28 15:32:38 -07:00
Eddie Hung
a45c09c8d1
Account for D port being a constant
2019-08-28 15:31:55 -07:00
Eddie Hung
1b08f861b6
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-28 15:31:48 -07:00
Eddie Hung
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
Eddie Hung
fc727fa5c9
Merge pull request #1334 from YosysHQ/clifford/async2synclatch
...
Add $dlatch support to async2sync
2019-08-28 12:36:06 -07:00
Eddie Hung
52c4655de3
No need to replace Q of slice since $shiftx is autoremove-d
2019-08-28 11:06:11 -07:00
Eddie Hung
11e3eb1009
More cleanup
2019-08-28 10:19:35 -07:00
Eddie Hung
86b538bd02
More cleanup
2019-08-28 10:11:09 -07:00
Eddie Hung
c4d1bd988b
Do not use default_params dict, hardcode default values, cleanup
2019-08-28 10:06:40 -07:00
Eddie Hung
c3e9627afe
Always generate if no match
2019-08-28 09:54:56 -07:00
Eddie Hung
0ebe2c9831
Rename test_pmgen arg xilinx_srl.{fixed,variable}
2019-08-28 09:27:03 -07:00
Eddie Hung
ba5d81c7f1
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-28 09:21:03 -07:00
Clifford Wolf
47ffbf554e
Fix typo
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:06:42 +02:00
Clifford Wolf
0fda0e821c
Add "paramap" pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:03:27 +02:00
Clifford Wolf
c499dc3e73
Add $dlatch support to async2sync
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 09:45:22 +02:00
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init
...
In sat: 'x' in init attr should be ignored
2019-08-28 00:18:14 +02:00
Eddie Hung
28133432be
Ignore all 1'bx in (* init *)
2019-08-27 09:24:59 -07:00
Marcin Kościelnicki
5fb4b12cb5
improve clkbuf_inhibit propagation upwards through hierarchy
2019-08-27 17:26:47 +02:00
Eddie Hung
9172d4a674
Missing close bracket
2019-08-26 21:02:52 -07:00
Eddie Hung
6b5e65919a
Revert "In sat: 'x' in init attr should not override constant"
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This reverts commit 2b37a093e9
.
2019-08-26 17:52:57 -07:00
Eddie Hung
54422c5bb4
Remove leftover header
2019-08-26 17:51:13 -07:00
Eddie Hung
e95fb24574
Improve xilinx_srl.fixed generate, add .variable generate
2019-08-26 17:49:08 -07:00
Eddie Hung
45c34c87ee
Account for maxsubcnt overflowing
2019-08-26 17:48:54 -07:00
Eddie Hung
b32d6bf403
Add xilinx_srl_pm.variable to test_pmgen
2019-08-26 17:44:57 -07:00
Eddie Hung
e574edc3e9
Populate generate for xilinx_srl.fixed pattern
2019-08-26 14:21:17 -07:00
Eddie Hung
cf9e017127
Add xilinx_srl_fixed, fix typos
2019-08-26 14:20:06 -07:00
Eddie Hung
a098205479
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-26 13:25:17 -07:00
Eddie Hung
7911143827
Create new $__XILINX_SHREG_ cell for variable length too
2019-08-23 18:15:49 -07:00
Eddie Hung
a048fc93e8
Do not allow Q of last cell of variable length SRL to be (* keep *)
2019-08-23 18:15:24 -07:00
Eddie Hung
ee9f6e6243
Also add first.Q to chain_bits since variable length
2019-08-23 18:14:06 -07:00
Eddie Hung
70ce3d0670
Do not enforce !EN_POLARITY on $dffe
2019-08-23 18:11:28 -07:00
Eddie Hung
188b49378a
Create new cell for fixed length SRL
2019-08-23 17:25:30 -07:00
Eddie Hung
e081303ee8
Cleanup FDRE matching
2019-08-23 17:23:52 -07:00
Eddie Hung
54488cfb82
Oops don't need a finally block
2019-08-23 16:39:37 -07:00
Eddie Hung
83e2d87fb8
Keep track of bits in variable length chain, to check for taps
2019-08-23 16:21:10 -07:00
Eddie Hung
f2d4814284
Don't forget $dff has no EN
2019-08-23 16:14:57 -07:00
Eddie Hung
2217d926a9
Same for variable length
2019-08-23 16:13:16 -07:00
Eddie Hung
b1caf7be5e
Filter on en_port for fixed length
2019-08-23 16:09:46 -07:00
Eddie Hung
513af10d77
Check clock is consistent
2019-08-23 15:18:26 -07:00
Eddie Hung
c762618783
Fix last_cell.D
2019-08-23 15:08:49 -07:00
Eddie Hung
ca5de78e76
Revert "Add a unique argument to pmgen's nusers()"
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This reverts commit 1d88887cfd
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2019-08-23 15:04:00 -07:00
Eddie Hung
e85e6e8d45
Revert "Fix polarity"
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This reverts commit 9cd23cf0fe
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2019-08-23 15:03:42 -07:00
Eddie Hung
9cd23cf0fe
Fix polarity
2019-08-23 14:49:34 -07:00
Eddie Hung
c2757613b6
Check for non unique nusers/fanouts
2019-08-23 14:32:36 -07:00
Eddie Hung
1d88887cfd
Add a unique argument to pmgen's nusers()
2019-08-23 14:32:17 -07:00
Eddie Hung
8ecfd55d5a
Update doc
2019-08-23 14:16:41 -07:00
Eddie Hung
3d7f4aa0c8
Remove (* init *) entry when consumed into SRL
2019-08-23 13:56:01 -07:00
Eddie Hung
48c424e45b
Cleanup
2019-08-23 13:46:05 -07:00
Eddie Hung
967a36c125
indo -> into
2019-08-23 13:16:50 -07:00
Eddie Hung
a1f78eab04
indo -> into
2019-08-23 13:15:41 -07:00
Eddie Hung
5939ffdc07
Forgot to slice
2019-08-23 13:06:59 -07:00
Eddie Hung
242b3083ea
Cope with possibility that D could connect to Q on same cell
2019-08-23 13:06:31 -07:00
Eddie Hung
18b64609c2
xilinx_srl to use 'slice' features of pmgen for word level
2019-08-23 12:22:06 -07:00
Eddie Hung
f4fd41d5d2
Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
2019-08-23 11:35:06 -07:00
Eddie Hung
78b7d8f531
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-23 11:32:44 -07:00
Eddie Hung
d672b1ddec
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-23 11:26:55 -07:00
Eddie Hung
619f2414e5
clkbufmap to only check clkbuf_inhibit if no selection given
2019-08-23 11:14:42 -07:00
Eddie Hung
4d89c3f468
Review comment from @cliffordwolf
2019-08-23 10:03:41 -07:00
Eddie Hung
6872805a3e
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-23 10:00:50 -07:00
Clifford Wolf
55bf8f69e0
Fix port hanlding in pmgen
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-23 16:26:54 +02:00
Clifford Wolf
adb81ba386
Add pmgen slices and choices
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-23 16:15:50 +02:00
Eddie Hung
51ffb093b5
In sat: 'x' in init attr should not override constant
2019-08-22 16:43:08 -07:00
Eddie Hung
2b37a093e9
In sat: 'x' in init attr should not override constant
2019-08-22 16:42:19 -07:00
Eddie Hung
53fed4f7e9
Actually, there might not be any harm in updating sigmap...
2019-08-22 16:16:56 -07:00
Eddie Hung
cfafd360d5
Add comment as per @cliffordwolf
2019-08-22 16:16:56 -07:00
Eddie Hung
8691596d19
Revert "Try way that doesn't involve creating a new wire"
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This reverts commit 2f427acc9e
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2019-08-22 16:16:34 -07:00
Eddie Hung
5ff75b1cdc
Try way that doesn't involve creating a new wire
2019-08-22 16:16:34 -07:00
Eddie Hung
e1fff34dde
If d_bit already in sigbit_chain_next, create extra wire
2019-08-22 16:16:34 -07:00
Eddie Hung
c50d68653d
Spelling
2019-08-22 16:06:36 -07:00
Eddie Hung
6e8fda8bf0
Add doc
2019-08-22 11:52:24 -07:00
Eddie Hung
cabadb85e2
Add copyright
2019-08-22 11:25:19 -07:00
Eddie Hung
36d94caec1
Remove `shregmap -tech xilinx` additions
2019-08-22 11:22:09 -07:00
Eddie Hung
9f3ed1726e
pmgen to also iterate over all module ports
2019-08-22 11:15:16 -07:00
Eddie Hung
74bd190d3b
Remove output_bits
2019-08-22 11:14:59 -07:00
Eddie Hung
231ddbf95c
Forgot to set ud_variable.minlen
2019-08-22 11:02:17 -07:00
Eddie Hung
61639d5387
Do not run xilinx_srl_pm in fixed loop
2019-08-22 10:51:04 -07:00
Eddie Hung
7188972645
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-22 10:32:54 -07:00